Vertical Memory String Architecture for High Density Storage
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in increasing storage capacity due to limitations in fine pattering and physical constraints, such as breakdown voltage, which are difficult to overcome with current photolithography techniques like ArF liquid immersion lithography, and three-dimensional integration is costly and impractical with EUV exposure.
Innovation Solution
A nonvolatile semiconductor memory device with a plurality of memory strings featuring a columnar semiconductor portion extending vertically from a substrate, accompanied by charge storage layers, insulators, and conductors, allowing for serially connected electrically rewritable memory cells, and a method of manufacturing involving layered conductors, penetrated holes, and specific insulator formations to optimize memory cell structure and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine pattering is pursued to increase storage capacity, then memory integration is improved, but manufacturing cost and technical difficulty increase due to limitations in photolithography resolution
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. Multiple memory cell layers are stacked vertically with columnar semiconductor portions extending through multiple gate electrode layers, enabling increased storage capacity without requiring finer lateral pattering. This vertical dimension expansion allows conventional photolithography to remain effective while achieving higher integration density.
2Quantity of substance
If fine pattering is pursued to increase storage capacity, then memory integration is improved, but manufacturing complexity increases due to need for EUV exposure
Solution Approach 1:
By stacking memory cell layers vertically, the patent achieves higher storage capacity without requiring EUV exposure. The three-dimensional structure allows multiple memory cells to be formed using conventional photolithography processes, thereby reducing manufacturing process complexity while increasing integration density.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically. Each layer contains columnar semiconductor portions and associated gate electrodes, forming independent but interconnected memory cells. This segmentation allows each layer to be manufactured using standard processes while the overall stack provides enhanced storage capacity.
3Quantity of substance
If three-dimensional integration is implemented to increase storage capacity, then memory integration is improved, but manufacturing cost increases due to expensive EUV exposure requirements
Solution Approach 1:
The patent implements three-dimensional integration by vertically stacking memory cell layers with columnar semiconductor portions extending through multiple gate electrode layers. This approach achieves increased storage capacity using conventional photolithography processes, avoiding the need for expensive EUV exposure while maintaining cost-effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory integration and operation by enabling finer pattering without the need for expensive EUV exposure, reducing physical limitations and improving data retention and write characteristics, while maintaining cost-effectiveness.
Implementation Method 1
a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge
Data Source
AI summary
A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.