Vertical Memory Stack and String Selection Layout for 3D Reliability
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Solution Overview
Problem
Reliable manufacturing of three-dimensionally arranged vertical non-volatile memory devices is challenging.
Innovation Solution
A vertical non-volatile memory device design featuring a memory cell region with a memory stack structure and an extension region, including specific arrangements of channel regions, gate dielectric layers, and gate lines, along with string selection structures, enhances manufacturing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are implemented, then data storage capacity is improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent divides the memory device into distinct regions: a memory cell region containing vertical memory stacks and an extension region containing string selection structures. This segmentation allows different parts of the device to be optimized for their specific functions, with the memory cell region focusing on high-density storage and the extension region on reliable signal routing, thereby maintaining manufacturing reliability while achieving high storage capacity.
Solution Approach 2:
The patent transitions from two-dimensional memory arrangement to three-dimensional vertical stacks, with channel holes extending in the vertical direction and gate lines arranged in multiple levels. This dimensional change enables significantly higher storage capacity per unit area while maintaining manufacturability through systematic vertical stacking of identical memory cell structures.
2Quantity of substance
If vertical memory stacks are used, then storage density is improved, but device complexity increases
Solution Approach 1:
The patent designs the memory cell region and extension region to share common structural elements and manufacturing processes. Both regions utilize similar gate dielectric layer configurations and channel hole structures, allowing the same fabrication procedures to be applied across the entire device, thereby reducing overall device complexity despite the three-dimensional architecture.
Solution Approach 2:
The patent implements nested structures where gate dielectric layers surround channel holes, and multiple memory cell stacks are arranged within a single memory block. The extension region's string selection structures are integrated alongside the memory cell region, creating a compact nested arrangement that achieves high storage density without proportionally increasing device complexity.
3Quantity of substance
If three-dimensional structure is implemented, then capacity per area is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different structural configurations to different regions: the memory cell region uses vertical stacked memory cells for high capacity, while the extension region uses string selection structures optimized for electrical connection. This local differentiation allows each region to be manufactured with precision optimized for its specific function, reducing overall manufacturing precision requirements compared to a uniform three-dimensional structure.
Data Source
AI summary
A vertical non-volatile memory device includes a memory cell region and an extension region. The memory cell region includes a memory stack structure, and the memory stack structure includes first channel regions in channel holes, first gate dielectric layers that extend around respective ones of the first channel regions, and first gate lines that extend around respective ones of the first gate dielectric layers. The memory cell region and the extension region each include a string selection structure in an upper portion thereof, and the string selection structure includes second channel regions in string selection line holes, gate dielectric layers on upper surfaces and both side surfaces of the second channel regions, and second gate lines that extend around respective ones of the second gate dielectric layers.