Vertical Memory String Structure for Signal Integrity
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Solution Overview
Problem
Conventional semiconductor storage devices face challenges in refining memory storage capacity due to limitations in photolithography technology and physical improvements, such as breakdown voltage, and there are concerns about signal reduction in three-dimensional memory cell arrangements with MONOS layers.
Innovation Solution
A non-volatile semiconductor storage device with memory strings featuring columnar semiconductor layers, surrounded by conductive layers functioning as floating gates and control electrodes, formed using polysilicon and insulation layers, with specific manufacturing processes to ensure reliable operation and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional manner to increase storage capacity, then integration density is improved, but signal reduction occurs due to charge transfer in MONOS layers
Solution Approach 1:
The patent extracts the problematic MONOS layer from the charge storage structure and replaces it with a simplified configuration using only a tunnel insulation layer and a charge storage layer. This removal eliminates the charge transfer issue between layers while maintaining the three-dimensional memory cell arrangement, thus preserving signal integrity while keeping high storage capacity.
Solution Approach 2:
The patent uses a composite structure consisting of a tunnel insulation layer and a charge storage layer formed directly on the semiconductor substrate. This composite material approach replaces the complex MONOS structure with a simpler two-layer composite that achieves the same charge storage function without the intermediate nitride layer that causes signal degradation.
2Manufacturing precision
If photolithography technology is refined to reduce device dimension, then integration density is improved, but manufacturing cost increases due to EUV exposure requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking. This dimensional change allows achieving high integration density without further reducing the lateral dimensions of individual devices, thereby avoiding the need for expensive EUV photolithography while maintaining cost-effective manufacturing processes.
3Quantity of substance
If device dimension is reduced to increase storage capacity, then integration density is improved, but breakdown voltage between devices deteriorates
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent increases storage capacity without reducing the lateral size of individual cells. This maintains adequate spacing between devices and preserves breakdown voltage characteristics while achieving higher integration density through the vertical dimension.
Data Source
AI summary
A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.