Vertical Memory Cell Strings With Charged Backside Insulator
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Solution Overview
Problem
Current memory cell architectures face challenges in optimizing current flow density and charge management within transistors, particularly in non-volatile and volatile memory cells, where charge carriers' distribution affects data retention and storage efficiency.
Innovation Solution
The proposed solution involves a vertical stack of alternating insulative and conductive tiers in memory cell arrays, with a charge-blocking region and charge-storage material extending along the control gates, and insulating material with net negative charge adjacent to the channel region, facilitating controlled charge passage and retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge-storage material and charge-blocking regions are added to improve charge management, then data retention is improved, but device complexity increases
Solution Approach 1:
The patent implements nesting by placing charge-storage material within the gate structure and charge-blocking regions at specific interfaces, creating a nested configuration where multiple functional elements are integrated within the transistor's gate region. This allows charge management functions to be embedded within the existing transistor architecture rather than adding separate external components.
Solution Approach 2:
The patent transitions from planar charge management to vertical/dimensional charge management by extending charge-storage material and charge-blocking regions through the gate thickness. This dimensional change allows charge to be managed in the vertical dimension alongside the horizontal channel control, improving retention without significantly increasing planar device footprint.
2Power
If insulating material with net negative charge is placed adjacent to the channel region, then current flow density near the gate insulator is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the insulating material with net negative charge directly with the gate insulator structure, forming an integrated multi-layer gate insulator system. This combining approach ensures that the charged insulating material is precisely positioned adjacent to the channel region through standard semiconductor fabrication processes, eliminating the need for separate precision placement steps.
Solution Approach 2:
The patent utilizes parameter changes by controlling the electrical charge state of the insulating material and its spatial distribution within the gate structure. By adjusting the charge density and positioning parameters during fabrication, the current flow density enhancement is achieved while maintaining compatibility with existing manufacturing tolerances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances current flow density closer to the gate insulator, improves charge management, and maintains data retention, thereby increasing the efficiency and reliability of memory cell operations.
Implementation Method 1
insulating material having net negative charge adjacent the backside of the channel region
Data Source
AI summary
A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.