Vertical Memory Structure for High-Density Semiconductor Storage
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Solution Overview
Problem
There is a need for semiconductor devices that can efficiently store high-capacity data, and existing two-dimensional memory cell arrangements are limited in their storage capacity, prompting the exploration of three-dimensional memory structures to enhance data storage capabilities.
Innovation Solution
A semiconductor device with a vertical memory structure that includes an insulating core region, a channel layer, and dielectric structures, along with conductive and insulating layers, is developed. This structure penetrates through a stack of interlayer insulating layers and gate layers, with conductive patterns and contact plugs connecting the memory cells, enabling increased storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional memory cell arrangement is used, then device structure is simple, but data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical memory structure. The vertical memory structure includes a channel layer extending in the vertical direction, surrounded by dielectric structures and gate layers at different heights, enabling data storage in the third dimension (vertical direction) while maintaining planar footprint, thus significantly increasing storage capacity without proportionally increasing device area.
2Quantity of substance
If vertical memory structure is implemented, then storage density increases, but contact resistance may worsen
Solution Approach 1:
The vertical memory structure is segmented into multiple functional regions along the vertical direction, with gate layers at different heights (first gate layer, second gate layer, third gate layer) and corresponding contact structures. This segmentation allows for optimized electrical contact at each level, with source contact plugs and bit line contact plugs positioned at specific heights to minimize resistance while maintaining vertical stacking for high density.
Solution Approach 2:
Dielectric structures serve as intermediary elements between the channel layer and gate layers, providing both electrical isolation and mechanical support. The dielectric structures fill spaces between vertical memory structures and provide pathways for contact plugs to reach the channel layer at appropriate heights, facilitating low-resistance contacts while maintaining the vertical high-density architecture.
3Quantity of substance
If multiple gate layers are stacked vertically, then storage capacity increases, but manufacturing complexity increases
Solution Approach 1:
The patent implements multiple gate layers stacked vertically around the channel layer, with each gate layer positioned at a different height. This vertical stacking approach increases storage capacity by utilizing the third dimension, while the systematic arrangement of gate layers (first, second, third gate layers) and their corresponding dielectric structures provides a manufacturable pattern that can be formed using sequential deposition and etching processes.
Data Source
AI summary
A semiconductor device includes an upper structure on a lower structure. The upper structure includes a stack structure including gate layers, a vertical memory structure penetrating the stack structure, a bit line electrically connected to the vertical memory structure and below the stack structure, and a conductive pattern electrically connected to the vertical memory structure and on the stack structure. The vertical memory structure includes an insulating core region, a first pad pattern electrically connected to the conductive pattern on the insulating core region, a dielectric structure on a side surface of the insulating core region and a side surface of the first pad pattern, and a channel layer. The channel layer includes a first portion contacting the dielectric structure and a second portion extending from the first portion and between a lower surface of the first pad pattern and an upper surface of the insulating core region.