Vertical Memory Sub-Stacks With Doped Channel Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and reliability while maintaining integration efficiency.
Innovation Solution
A semiconductor device design featuring vertically stacked sub-stacks with alternating interlayer insulating layers and conductive patterns, including a vertical channel with an impurity region and data storage patterns, enhances data storage capacity and reliability by utilizing impurity-doped channels and multiple erase control lines for efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase capacity, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking, forming multiple sub-stacks (first sub-stack, second sub-stack, etc.) that are vertically arranged. This dimensional change enables significantly increased data storage capacity by utilizing the vertical space, with each sub-stack containing multiple conductive patterns and interlayer insulating layers stacked alternately.
Solution Approach 2:
The memory device is divided into multiple independent sub-stacks (first sub-stack, second sub-stack, third sub-stack, etc.), each with its own conductive patterns and interlayer insulating layers. This segmentation allows for modular design and independent control of each sub-stack, managing the complexity through organization while maintaining high capacity.
2Quantity of substance
If vertically stacked sub-stacks are used to increase capacity, then data storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces intermediate insulating layers (first intermediate insulating layer, second intermediate insulating layer, etc.) positioned between adjacent sub-stacks. These intermediate insulating layers serve as mediators that electrically isolate and physically separate the vertically stacked sub-stacks, enabling precise control of electrical connections and signal integrity while maintaining the vertical stacking structure.
Solution Approach 2:
The patent applies different material properties and structural characteristics to specific regions. The intermediate insulating layers are strategically placed at critical interfaces between sub-stacks to provide localized electrical isolation and mechanical support, while the conductive patterns within each sub-stack maintain specific conductivity characteristics for data storage operations.
3Reliability
If impurity regions are added to vertical channels for better control, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent modifies the electrical parameters of the vertical channels by introducing impurity regions with specific doping concentrations and types (n-type or p-type). These parameter changes in the channel region enable improved carrier concentration and electrical control, enhancing the reliability of data storage operations while maintaining a relatively simple structural addition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves data storage capacity and reliability by enabling efficient data storage operations through vertically integrated structures and advanced erase control mechanisms, optimizing performance and integration.
Implementation Method 1
the vertical channel includes an impurity region adjacent to the intermediate insulating layer, the impurity region doped with impurities of a first conductive type
Data Source
AI summary
A semiconductor device and an electronic system are provided. The semiconductor device includes a substrate, a first sub-stack including first interlayer insulating layers and first conductive patterns alternately stacked on the substrate, a second sub-stack including second interlayer insulating layers and second conductive patterns alternately stacked on the first sub-stack, an intermediate insulating layer between the first and second sub-stacks, a vertical channel penetrating the first and second sub-stacks and the intermediate insulating layer, a first data storage pattern penetrating the first sub-stack and surrounding a first vertical portion of the vertical channel, and a second data storage pattern penetrating the second sub-stack and surrounding a second vertical portion of the vertical channel, wherein the vertical channel includes an impurity region adjacent to the intermediate insulating layer, the impurity region doped with impurities of a first conductive type.