Vertical Memory Device Substrate Control Circuit Integration
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Solution Overview
Problem
As memory devices become more multi-functional and require higher integration, existing memory devices face challenges in achieving improved electrical characteristics and increased integration while managing complex operating circuits and wiring structures.
Innovation Solution
A vertical memory device is designed with a substrate control circuit that outputs a bias voltage to the upper substrate, divided into regions to overlap with the memory cell array, and includes substrate contact plugs for electrical connection, allowing for efficient bias voltage application and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell sizes are reduced for higher integration, then integration density increases, but operating circuits and wiring structures become more complex
Solution Approach 1:
The patent transitions from planar memory cell arrangement to a vertical three-dimensional structure, stacking memory cells and bit lines in multiple layers. This dimensional change allows higher integration density without proportionally increasing the complexity of operating circuits, as the vertical stacking efficiently utilizes space while maintaining manageable circuit interconnections through substrate contact plugs and controlled wiring layers.
2Reliability
If more substrate contact plugs are added to improve electrical connection, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
The patent strategically positions substrate contact plugs at specific locations where they are most needed for electrical connection, rather than uniformly distributing them. The wiring structure is designed to route connections efficiently to these localized contact points, improving electrical characteristics while minimizing the overall number of contact plugs and wiring complexity.
3Device complexity
If bias voltage application structure is simplified, then device complexity decreases, but resistance in bias voltage application increases
Solution Approach 1:
The substrate acts as an intermediary element that facilitates bias voltage application to the memory cell array. By applying bias voltage to the substrate, which is in direct contact with the memory cells through the vertical structure, the patent achieves low-resistance voltage application without requiring complex dedicated wiring structures, thus simplifying the overall bias voltage application architecture.
Data Source
AI summary
A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.