Vertical Non-Volatile Memory with Thermoelectric Heat Dissipation
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in maintaining stable operating temperatures, particularly as storage volumes increase, leading to the need for efficient heat dissipation methods.
Innovation Solution
A vertical non-volatile memory device incorporating a thermoelectric device with n-type and p-type semiconductor pillars, which are electrically connected and used to dissipate heat when the temperature exceeds a set reference, thereby maintaining stable operating temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If storage volume is increased in non-volatile memory devices, then capacity is improved, but heat dissipation becomes more difficult and operating temperature stability deteriorates
Solution Approach 1:
The patent transitions from planar transistor structures to vertical transistor structures, moving the memory architecture into the third dimension. This vertical configuration increases storage capacity while improving heat dissipation by reducing the thermal path length and enabling better thermal management at the chip level
Solution Approach 2:
The patent changes the physical parameters of the memory device by implementing vertical channel structures and stacked configurations, which alter the thermal and electrical characteristics to simultaneously achieve higher storage density and improved temperature stability
2Quantity of substance
If vertical transistor structure is used to increase storage volume, then capacity is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory device into distinct functional regions including cell array areas and extension areas, with separate vertical channel structures and thermoelectric devices. This segmentation allows for modular manufacturing and simplifies the fabrication process despite the vertical architecture
Solution Approach 2:
The vertical channel structures serve multiple functions simultaneously: they provide the memory storage function, act as thermal management pathways, and enable extended electrode connections. This multi-functionality reduces the need for separate components and simplifies the overall device architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the thermoelectric device effectively dissipates heat from the memory device, ensuring stable operating temperatures and enhancing the reliability and performance of the device.
Implementation Method 1
a thermoelectric device on the substrate, the thermoelectric device including at least two semiconductor pillars extending perpendicular to a top surface of the substrate, and when the temperature measured using the at least one temperature sensor exceeds a set reference temperature, the n-type semiconductor pillar is connected, through a top end thereof, to a power source and the p-type semiconductor pillar is connected, through a top end thereof, to ground, such that the thermoelectric device is turned on and heat from the substrate is dissipated through the at least two semiconductor pillars
Data Source
AI summary
A vertical non-volatile memory device capable of stably maintaining an operating temperature in a chip level, a semiconductor package including the memory device, and a heat dissipation method of the memory device. The vertical non-volatile memory device includes a substrate on which a cell array area and an extension area are defined, a vertical channel structure formed on the substrate, a thermoelectric device including at least two semiconductor pillars formed on the substrate, and a stacked structure on the substrate. The stacked structure includes a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars. The at least two semiconductor pillars include an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.