Vertical Memory Cell Array Through-Electrode Layout for Noise Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit devices face challenges in providing improved electrical characteristics and data integrity due to increased complexity and reduced size of memory cells, which affect signal connections and overall integration density.
Innovation Solution
The integrated circuit device incorporates a conductive plate with through holes arranged in a zigzag pattern, connecting conductive lines to the peripheral circuit structure through the cell array structure, allowing for uniform cell current flow and reduced noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell size is reduced to increase integration density, then integration density is improved, but electrical characteristics and data integrity deteriorate
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to 3D vertical stacking architecture. Memory stacks are formed vertically over the substrate, with multiple tiers of memory cells stacked along the vertical direction. This dimensional change allows significant increase in integration density while maintaining adequate electrical characteristics through controlled signal paths and isolation structures.
Solution Approach 2:
The memory array is divided into multiple independent memory stacks, each containing multiple tiers of memory cells. Through electrodes are strategically positioned to connect bit lines to specific memory cell tiers, creating segmented signal paths. This segmentation isolates electrical interference between adjacent memory cells, improving data integrity while maintaining high integration density.
2Productivity
If memory cell size is reduced to increase integration density, then integration density is improved, but noise increases
Solution Approach 1:
Isolation structures are introduced as intermediary elements between adjacent memory stacks and tiers. These isolation structures physically separate conductive paths and prevent electrical interference and noise coupling between neighboring memory cells. This mediation allows high integration density through vertical stacking while suppressing noise through effective electrical isolation.
Solution Approach 2:
By moving to 3D vertical stacking with multiple tiers, the patent increases the physical separation distance between adjacent memory cells in the horizontal plane. This spatial separation in the vertical dimension reduces capacitive coupling and noise interference between cells, allowing high integration density without proportional noise increase.
3Productivity
If complex wiring structures are used to support reduced memory cell size, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension to route bit lines through through electrodes that extend through isolation structures to reach specific memory cell tiers. This vertical routing approach simplifies the wiring structure compared to planar routing, as it allows direct connection to stacked memory cells without requiring complex lateral interconnect layers, thereby reducing overall device complexity while maintaining high integration density.
Data Source
AI summary
An integrated circuit device includes; a peripheral circuit structure, a cell array structure including gate lines overlapping the peripheral circuit structure and disposed on the peripheral circuit structure in a vertical direction, a conductive plate interposed between the peripheral circuit structure and the cell array structure and including through holes, conductive lines spaced apart from the conductive plate with the cell array structure interposed between the conductive lines and the conductive plate, and through electrodes connected to the conductive lines and extending to the peripheral circuit structure through the cell array structure and the through holes. The through holes include a first through holes arranged along a first straight line extending in a first horizontal direction, and second through holes arranged along a second straight line extending in parallel with the first straight line and spaced apart from the first straight line in a second horizontal direction.