Vertical Memory Array Transistor Configurations for Leakage Control
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Solution Overview
Problem
Existing memory devices with single-transistor architectures experience significant leakage and increased power consumption due to large voltage differentials across deactivated transistors, which can disrupt access operations and reduce accuracy.
Innovation Solution
Implementing a multi-transistor architecture, such as a two-transistor architecture, where conductive pillars are coupled with different bit lines using separate transistors to reduce voltage differentials across deactivated transistors, thereby minimizing leakage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-transistor architecture is used to couple conductive pillars with bit lines, then device complexity is reduced, but leakage increases and power consumption increases due to large voltage differentials across deactivated transistors
Solution Approach 1:
The patent divides the single transistor into two separate transistors (first transistor and second transistor), each coupled to different bit lines. This segmentation allows independent control of voltage differentials across each transistor, reducing leakage and power consumption while maintaining architectural simplicity through modular design.
Solution Approach 2:
The patent applies different configurations to different transistors based on their specific functions. The first transistor is configured for coupling with a first bit line while the second transistor is configured for coupling with a second bit line, allowing optimized local performance for each transistor's specific role in reducing voltage differential and leakage.
2Device complexity
If a single-transistor architecture is used, then device complexity is reduced, but leakage increases due to large voltage differentials across deactivated transistors
Solution Approach 1:
By segmenting the single transistor into two separate transistors, each with its own bit line connection, the patent reduces the voltage differential across any single deactivated transistor. This segmentation prevents the large voltage differentials that cause harmful leakage currents in single-transistor architectures.
Solution Approach 2:
The patent introduces an additional transistor as an intermediary element between the conductive pillar and the bit line system. This intermediary transistor works in conjunction with the first transistor to control and reduce voltage differentials, thereby minimizing leakage through the bit line structure.
3Device complexity
If a single-transistor architecture is used, then device complexity is reduced, but access operation accuracy decreases due to leakage disruptions
Solution Approach 1:
The patent segments the transistor function into two separate transistors that can independently control their states. This segmentation enables precise control of voltage differentials during access operations, preventing leakage-induced disruptions and maintaining high measurement and access accuracy.
Solution Approach 2:
The patent changes the voltage differential parameter across transistors by introducing a second transistor with a different bit line connection. This parameter change reduces the voltage differential magnitude, thereby minimizing leakage effects that would otherwise disrupt access operation accuracy.
Data Source
AI summary
Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.