Vertical Memory Transistor Structure for Higher Storage Density
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Solution Overview
Problem
Existing memory technologies face challenges in improving storage density without compromising transistor performance due to the narrow channel and short channel effects associated with reducing the size of planar transistors.
Innovation Solution
A method for forming a semiconductor structure that includes forming sacrificial layers and active layers on a substrate, etching to create active lines and gaps, filling with conductive material to form bit lines, and patterning to create vertical transistors with reduced layout size, allowing for increased integration and storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel size of the transistor is reduced to improve storage density, then the storage density of the memory is improved, but the transistor performance deteriorates due to narrow channel effect and short channel effect
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel to extend in the vertical direction while maintaining adequate horizontal dimensions, thereby improving storage density without suffering from narrow channel and short channel effects that plague scaled-down planar transistors.
Solution Approach 2:
The patent segments the transistor structure into distinct vertical layers including source region, channel region, and drain region arranged sequentially in the vertical direction. This segmentation allows each region to be optimized independently while maintaining proper electrical isolation and functionality, resolving the performance-density tradeoff.
2Quantity of substance
If the size of the transistor is reduced to improve storage density, then the integration level is improved, but the manufacturing precision requirements increase due to narrower channel dimensions
Solution Approach 1:
By orienting the channel vertically rather than horizontally, the patent reduces the lateral dimension requirements while maintaining adequate channel length for proper electrical characteristics. This dimensional change relaxes manufacturing precision requirements for channel width control while achieving higher integration density.
Solution Approach 2:
The patent applies different material compositions and structural characteristics to different vertical regions of the transistor. The source and drain regions have different properties than the channel region, allowing each to be optimized for its specific function while maintaining overall device performance and reducing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of vertical transistors with reduced area and channel width, enhancing integration level and storage density while maintaining transistor performance.
Implementation Method 1
the active layer and the sacrificial layer are etched up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along a first direction
Implementation Method 2
a conductive material is filled in the gap to form a bit line extending along the first direction
Implementation Method 3
the active lines are patterned to form a plurality of separate active pillars that are arrayed along the first direction and a second direction
Data Source
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AI summary
A semiconductor structure, a method for forming the semiconductor structure and a memory are provided. The method includes: providing a substrate, wherein a sacrificial layer and an active layer located on the sacrificial layer are formed on the substrate; etching the active layer and the sacrificial layer up to a surface of the substrate to form a plurality of active lines arranged in parallel and extending along a first direction; filling an opening located between two adjacent ones of the active lines to form a first isolating layer; etching an end of the active lines to form an opening hole; removing the sacrificial layer along the opening hole, to form a gap between a bottom of the active lines and the substrate; filling a conductive material in the gap to form a bit line extending along the first direction; patterning the active lines to form a plurality of separate active pillars that are arrayed along the first direction and a second direction; and forming semiconductor pillars on top surfaces of respective ones of the active pillars. The method for forming the semiconductor structure is favorable for improving the integration level and performance of a transistor and improving the storage density of the memory.