Vertical Memory Transistor With Wide Bandgap Semiconductor
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Solution Overview
Problem
Conventional DRAM memory devices suffer from short data retention periods due to leakage currents in transistors and require frequent refresh operations, and they face challenges in further miniaturization beyond reducing circuit line widths.
Innovation Solution
A memory device design featuring a cell transistor with extremely low leakage current, where the source and drain are stacked vertically at the intersection of bit and word lines, and a capacitor is stacked above the transistor, using a semiconductor material with a wider band gap than silicon to reduce off-state current and increase data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistors or RCAT are used in DRAM, then the memory device can be manufactured with existing processes, but the data retention period is short due to leakage current and frequent refresh operations are required
Solution Approach 1:
The patent changes the material parameter of the semiconductor layer from conventional silicon to wide band gap semiconductor (such as silicon carbide or gallium nitride), which fundamentally alters the electrical characteristics to achieve extremely low off-state current and long data retention period without requiring frequent refresh operations
2Area of stationary object
If conventional planar transistors are used, then the manufacturing process is simple, but the memory element area is large (8 F2 or more)
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a three-dimensional vertical structure where the channel extends in the vertical direction, allowing the memory element to occupy minimal substrate area (4 F2) while maintaining manufacturing feasibility
Solution Approach 2:
The patent implements a stacked configuration where the capacitor is positioned directly above the transistor, and the transistor itself has a vertical channel structure, creating a nested three-dimensional arrangement that minimizes the footprint of the memory element
3Productivity
If circuit line width is reduced to increase integration density, then more memory elements can be packed, but manufacturing precision requirements increase and leakage current problems worsen
Solution Approach 1:
By moving to a vertical channel structure, the patent decouples integration density from horizontal line width reduction, allowing high density to be achieved through vertical stacking rather than continuous miniaturization of horizontal features
4Reliability
If silicon semiconductor is used in the transistor channel, then the transistor can be manufactured with standard processes, but the off-state current is high and data retention is limited
Solution Approach 1:
The patent changes the fundamental material parameter from silicon to wide band gap semiconductor, which provides inherently lower off-state current due to the wider band gap, thereby improving data retention characteristics while accepting the need for specialized manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a significantly smaller memory element area and longer data retention period, reducing the need for frequent refresh operations and enabling higher integration density.
Implementation Method 1
The semiconductor layer in the cell transistor is formed using a semiconductor material having a wider band gap than silicon
Data Source
AI summary
A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.