Vertical Memory Device Trenches Dopant Regions
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Solution Overview
Problem
Vertical memory cells face issues such as charge punch through, asymmetric threshold voltages, and asymmetric programming speeds, leading to reduced performance and memory density.
Innovation Solution
A memory device with a substrate having trenches, conductive layers, charge storage layers, and dopant regions of different conductive types, where the dopant regions are strategically positioned to prevent charge punch through and ensure symmetric programming speeds, including forming first and second dopant regions with specific ion implantation energies and concentrations to enhance electric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical memory cell structure is used to increase memory density, then storage capacity is improved, but charge punch through occurs between vertically adjacent bits causing leakage current
Solution Approach 1:
The patent divides the vertical memory cell into multiple horizontal sections by introducing alternating N-type and P-type dopant regions at different depths. This segmentation creates discrete storage zones that prevent charge carriers from moving vertically between adjacent memory bits, thereby eliminating charge punch through while maintaining high memory density.
Solution Approach 2:
The patent introduces P-type dopant regions as intermediary layers between N-type storage regions in vertically adjacent memory bits. These P-type regions act as blocking barriers that prevent charge carriers from punching through to adjacent bits, thus solving the leakage current problem while preserving the vertical cell structure's high density advantage.
2Quantity of substance
If a vertical memory cell structure is used to increase memory density, then storage capacity is improved, but asymmetric threshold voltages occur reducing device performance
Solution Approach 1:
The patent deliberately introduces asymmetric dopant region configurations where P-type and N-type regions are alternately positioned at different horizontal locations for adjacent memory bits. This controlled asymmetry in dopant placement creates symmetric threshold voltage characteristics by balancing the electrical fields across vertically adjacent cells, thereby improving device performance while maintaining high memory density.
3Quantity of substance
If a vertical memory cell structure is used to increase memory density, then storage capacity is improved, but asymmetric programming speeds occur reducing device performance
Solution Approach 1:
The patent employs asymmetric positioning of P-type and N-type dopant regions in vertically adjacent memory bits, where the horizontal locations of dopant regions alternate between adjacent bits. This asymmetric configuration creates symmetric programming speeds by balancing the charge injection characteristics across vertical neighbors, thereby improving device performance while preserving high memory density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents charge punch through and achieves symmetric threshold voltages and programming speeds, enhancing memory device performance and increasing storage density.
Implementation Method 1
forming first and second dopant regions with specific ion implantation energies and concentrations
Data Source
AI summary
A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.