Vertical Memory Device Manufacturing via Unified Protection Layer
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Solution Overview
Problem
The complexity of manufacturing vertical memory devices with existing technologies leads to intricate processes, making it challenging to simplify the formation of vertical memory devices with distinct cell and peripheral regions.
Innovation Solution
A vertical memory device design that includes a substrate with channels extending perpendicular to the surface, charge storage structures on channel sidewalls, gate electrodes spaced apart, and a protection layer pattern covering semiconductor structures, along with sacrificial layers and insulating interlayers, allows for simplified manufacturing by forming a pyramid-shaped stack structure and protecting peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertical memory devices are formed with distinct cell and peripheral regions using existing technologies, then the device functionality is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines the formation of protection layers for peripheral circuits and sacrificial layers for cell regions into a single unified process step. A single layer is deposited across the entire substrate and then selectively removed in different regions, merging two previously separate manufacturing processes into one, thereby reducing process complexity while maintaining distinct functional regions
Solution Approach 2:
The patent segments the substrate into distinct cell and peripheral regions and applies different processing sequences to each segment. The protection layer is selectively removed in peripheral regions while being retained in cell regions, allowing differentiated treatment of different device regions within a unified process framework
2Reliability
If separate processes are used for forming vertical memory cells and peripheral circuits, then the structural requirements are met, but the manufacturing efficiency decreases
Solution Approach 1:
The patent merges the formation processes of protection layers and sacrificial layers into a single deposition step followed by selective removal. This combined process reduces the total number of manufacturing steps while ensuring that both peripheral circuits and memory cells meet their respective structural requirements through region-specific processing
3Shape
If multiple layers are formed alternately and repeatedly, then the pyramid-shaped stack structure is achieved, but the manufacturing steps increase
Solution Approach 1:
The patent performs preliminary deposition of protection and sacrificial layers across the entire substrate before any selective removal or further processing. This preliminary action establishes the base structure that will subsequently be differentiated by region, reducing the need for repeated deposition cycles and simplifying the overall manufacturing sequence
Data Source
AI summary
A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.