Vertical Memory Cell Structure With Upper Via Substrate Interconnect
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Solution Overview
Problem
Semiconductor devices face challenges in increasing integration density and reliability while processing high-capacity data, particularly in achieving efficient vertical transistor structures.
Innovation Solution
A semiconductor device design featuring a peripheral circuit region and a memory cell region with stacked gate electrodes, channel structures, and interconnection structures, including a third interconnection structure with an upper via extending from the second substrate and a lower interconnection structure connected to the first substrate, enhancing electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical transistor structure is adopted to increase integration density, then the integration density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical transistor structure by changing the dimensional orientation of the channel. The channel extends in the vertical direction (thickness direction of the semiconductor layer) rather than horizontally, enabling higher integration density by utilizing the third dimension for device stacking and compact layout.
Solution Approach 2:
The vertical transistor structure is divided into distinct functional segments including the semiconductor layer with channel, source and drain regions, gate electrode, and insulating layers. This segmentation allows for modular manufacturing processes and facilitates the complex vertical architecture by breaking it down into manageable fabrication steps.
2Quantity of substance
If multiple substrates are stacked to increase integration density, then the integration density is improved, but the reliability of electrical connections between substrates deteriorates
Solution Approach 1:
The patent merges the first substrate and second substrate into an integrated stacked structure where the second substrate is positioned on the first substrate with vertical transistors formed across both substrates. The source and drain regions extend through both substrates, creating unified electrical pathways that enhance connection reliability while maintaining high integration density.
Solution Approach 2:
The patent introduces an interconnection structure including conductive layers and insulating layers as intermediaries between the first and second substrates. These intermediary structures provide reliable electrical connections and mechanical support, ensuring signal integrity and structural stability across the stacked substrate architecture.
Data Source
AI summary
A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.