Vertical Memory Gate Via Insulation to Prevent Gate Shorts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In VNAND flash memory devices, contact plugs can inadvertently contact underlying gate electrodes, leading to electrical shorts between the gate electrodes, which necessitates a method to prevent such electrical shorts.
Innovation Solution
The vertical memory device incorporates gate electrodes stacked in a staircase shape with conductive through vias that are electrically insulated from underlying gate electrodes by insulation structures, allowing for electrical connection to conductive pads without the need for additional upper wiring, thus preventing electrical shorts and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are extended to contact underlying gate electrodes, then electrical connection is achieved, but electrical shorts occur between gate electrodes
Solution Approach 1:
The patent introduces an insulation structure as an intermediary element positioned between the contact plug and the underlying gate electrodes. This insulation layer acts as a mediator that allows the contact plug to extend through the gate electrodes without creating direct electrical contact with them, thereby preventing electrical shorts while maintaining the intended electrical connection functionality
Solution Approach 2:
The patent segments the contact plug structure by dividing it into functionally distinct regions: a first portion that electrically contacts the gate electrode and a second portion that extends through underlying gate electrodes but is electrically isolated from them by the insulation structure. This segmentation allows different portions of the same component to have different electrical relationships with surrounding structures
2Reliability
If additional upper wiring is added to prevent electrical shorts, then electrical isolation is achieved, but device complexity increases
Solution Approach 1:
Instead of adding more wiring layers in the horizontal plane to achieve electrical isolation, the patent moves the isolation function to the vertical dimension by introducing an insulation structure that extends through the gate electrodes. This dimensional shift eliminates the need for additional upper wiring while maintaining electrical isolation
Solution Approach 2:
The patent extracts the electrical isolation function from the wiring system and places it directly at the contact plug location through the insulation structure. By taking out the isolation requirement from the upper wiring layer and implementing it locally at the contact point, the need for additional complex wiring is eliminated
3Reliability
If contact plugs are restricted to avoid electrical shorts, then electrical short prevention is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the parameter of electrical conductivity by introducing the insulation structure, which transforms the contact plug's relationship with underlying gate electrodes from conductive to insulating. This parameter change allows the contact plug to maintain its extended geometry without requiring precise alignment control, as the insulation structure ensures electrical isolation regardless of minor positioning variations
Data Source
AI summary
A vertical memory device includes gate electrodes, a channel, a first conductive through via, and insulation structures. The gate electrodes are spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate, and may be stacked in a staircase shape. The channel extends through the gate electrodes in the first direction. The first conductive through via extends through a conductive pad of a first gate electrode among the gate electrodes and is electrically connected thereto. The first conductive through via extends through second gate electrodes from among the gate electrodes that are under the first gate electrode. The insulation structures are formed between the first conductive through via and sidewalls of each of the second gate electrodes, and electrically insulates the first conductive through via from each of the second gate electrodes.