3D Vertical Memory Cell Voltage Control for Erase Disturbance
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Solution Overview
Problem
Current two-dimensional non-volatile memory devices face limitations in integration density, prompting the development of three-dimensional memory devices with vertically stacked memory cells, where improving operation characteristics such as preventing erase disturbance and ensuring accurate read operations is crucial.
Innovation Solution
A non-volatile memory device design featuring semiconductor pillars with stacked memory cells, bit and source lines, and switches controlling voltage supply to source lines, allowing for independent voltage management during program, erase, and read operations, thereby preventing erase disturbance and ensuring accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional non-volatile memory devices are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking of memory cells along semiconductor pillars. Multiple memory cells are stacked in the vertical direction, enabling higher integration density while maintaining manufacturability through established semiconductor processing techniques for vertical structures
2Quantity of substance
If three-dimensional vertically stacked memory cells are implemented, then integration density improves, but operation control complexity increases
Solution Approach 1:
The patent divides the memory device into multiple independent memory blocks, each with its own source line and control switches. This segmentation allows independent voltage control and operation of each memory block, simplifying the control logic despite the three-dimensional structure by enabling selective access and operation of specific blocks without affecting others
3Reliability
If independent voltage control for each memory block is implemented, then erase disturbance is prevented, but device complexity increases
Solution Approach 1:
The patent introduces switch elements as intermediary components between voltage sources and source lines. These switches act as mediators that selectively connect or disconnect voltage sources to specific source lines, enabling precise control of voltage application to individual memory blocks and preventing erase disturbance without requiring complex direct control mechanisms
Data Source
AI summary
A non-volatile memory device includes: a semiconductor pillar stretched perpendicularly to a substrate; a plurality of memory cells stacked along the semiconductor pillar; a bit line coupled with a first end of the semiconductor pillar; a first source line coupled with one of the first end and a second end of the semiconductor pillar; a second source line disposed over the bit line and the first source line; a first switch having a first end coupled with the first source line and a second end coupled with a first voltage supplier, and controlling whether to supply a first voltage to the first source line; and a second switch having a first end coupled with the first source line and a second end coupled with the second source line, and controlling whether or not to supply a second voltage supplied from the second source line to the first source line.