Vertical Memory Device Wafer Bonding Layout
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Solution Overview
Problem
The increasing degree of integration and operating speed of memory devices lead to increased delays in voltage transfer and signal propagation, while the demand for smaller sizes and higher capacities results in larger occupation areas for control circuits, necessitating an efficient layout utilization method.
Innovation Solution
A memory device configuration with a cell wafer having a memory cell array, bonded to first and second logic wafers that control the array, where the logic wafers are positioned on opposite sides of the cell wafer, allowing for separate fabrication and reduced manufacturing steps, and overlapping circuit structures to optimize space and reduce delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the degree of integration and operating speed are increased, then the memory device performance is improved, but the delays in voltage transfer and signal propagation increase
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional vertical structure where the memory cell array extends in the vertical direction with multiple stacked layers. This dimensional change allows shorter horizontal signal paths while maintaining high integration, thereby reducing voltage transfer delays despite increased operating speed requirements
2Quantity of substance
If the demand for smaller sizes and higher capacities is met, then the memory device density is improved, but the occupation areas for control circuits increase
Solution Approach 1:
The control circuits are distributed across multiple vertical layers and integrated alongside the memory cell array in the vertical dimension. This allows the control circuits to occupy less planar area while still providing full control functionality for the high-capacity memory array, effectively reducing the occupation area footprint
Solution Approach 2:
The patent implements a nested structure where control circuits are integrated within and around the memory cell array in the vertical stacking architecture. The control circuits are positioned in different layers and can be nested between memory layers or integrated at the edges, allowing efficient space utilization and reduced overall occupation area
3Device complexity
If the logic circuits are integrated with the memory cell array in a single wafer, then the device complexity is reduced, but the manufacturing flexibility and productivity are decreased
Solution Approach 1:
The patent divides the memory device into separate wafer-level modules: a memory cell array wafer and logic circuit wafers that are bonded together. This segmentation allows each wafer to be fabricated independently using optimized processes, improving manufacturing flexibility and productivity while maintaining integrated functionality through wafer bonding
Solution Approach 2:
The patent introduces wafer bonding as an intermediary process that connects the memory cell array wafer with the logic circuit wafers. This bonding interface serves as a mediator that enables separate fabrication of the wafers while achieving integrated device functionality, thus improving manufacturing efficiency without sacrificing structural integration
Data Source
AI summary
A memory device includes a cell wafer including a memory cell array; a first logic wafer bonded to one surface of the cell wafer, and including a first logic circuit which controls the memory cell array; and a second logic wafer bonded to the other surface of the cell wafer which faces away from the one surface, and including a second logic circuit which controls the memory cell array.