Vertical Memory Word Line Interconnect via Dimensional Shift
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Solution Overview
Problem
In vertical non-volatile memory devices, the complex layout of connecting wirings on word lines in VNAND flash memory devices limits the available space for upper wirings, complicating the electrical connection between word lines.
Innovation Solution
The design eliminates the need for upper wirings by electrically connecting word lines within the same word line block using conductive connection portions, allowing for a more straightforward layout and increased space on the substrate for other components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connecting wirings are disposed on contact plugs on word lines in VNAND flash memory, then word lines can be electrically connected, but the wiring layout becomes complicated and space is limited
Solution Approach 1:
The patent transitions from planar wiring connections to three-dimensional vertical connections by stacking memory cells and word lines in multiple layers. Word lines are connected through vertical vias and contact plugs that extend through insulating layers, enabling electrical connection in the vertical dimension rather than requiring complex lateral routing. This dimensional change simplifies the overall wiring layout while maintaining reliable electrical connections.
2Reliability
If connecting wirings are disposed on contact plugs on word lines, then word lines can be electrically connected, but available space for upper wirings is limited
Solution Approach 1:
The invention utilizes the vertical dimension to route connections through stacked layers. Contact plugs extend vertically through insulating layers to connect word lines at different levels, and upper wirings are disposed in higher layers with sufficient spacing. This vertical stacking approach preserves horizontal space while enabling comprehensive electrical connections through the third dimension.
Solution Approach 2:
The patent divides the memory structure into multiple stacked cell blocks, each with its own set of word lines and contact plugs. This segmentation allows independent wiring routing for each block and reduces interference between adjacent word lines, thereby increasing available space for upper wirings while maintaining reliable electrical connections within each segmented block.
3Reliability
If connecting wirings are disposed on contact plugs on word lines, then word lines can be electrically connected, but the layout becomes complicated
Solution Approach 1:
By moving electrical connections to the vertical dimension through stacked layers and vertical vias, the patent simplifies the lateral layout process. Standardized via holes and contact plug formations can be applied uniformly across multiple layers, reducing manufacturing complexity compared to custom lateral wiring routing while ensuring reliable electrical connections.
Data Source
AI summary
A vertical memory device is provided. The vertical memory device includes a substrate, first gate electrodes, a channel, first wirings, and second wirings. The substrate includes a cell region and a peripheral circuit region. The first gate electrodes are spaced apart from each other in a first direction on the cell region of the substrate, the first direction being substantially perpendicular to the substrate. The channel extends through a portion of the first gate electrodes in the first direction on the cell region. The first wirings are formed on the cell region, and are disposed at first levels that are higher in the first direction than gate electrode levels on which the first gate electrodes are respectively formed. The second wirings are formed on the peripheral circuit region, and are disposed at the first levels and at a second level that is higher than the gate electrode levels.