3D Vertical Memory Gate Stack Covering Word Line Cuts
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Solution Overview
Problem
The integration of two-dimensional memory devices is limited by high equipment costs and area constraints, hindering the economic feasibility and performance of integrated circuit devices, while three-dimensional vertical memory devices are desired for enhanced integration.
Innovation Solution
The design of a vertical memory device with a three-dimensional structure includes a gate layer that forms a cover structure over the word line cut, improving structural stability and reducing the likelihood of cracks without additional processing steps, thereby enhancing the integration and economic feasibility of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If two-dimensional memory device integration is pursued, then manufacturing area and equipment cost are reduced, but integration density and performance are limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical memory structures by stacking multiple memory cell layers vertically. This dimensional change allows significantly higher integration density within the same chip die area, as memory cells are arranged in multiple stacked layers rather than a single plane, effectively multiplying the storage capacity per unit area.
2Ease of operation
If word line cuts are made in vertical memory devices, then connectivity is improved, but crack defects occur reducing reliability
Solution Approach 1:
The patent applies a protective layer (such as a dielectric or sacrificial layer) over the word line cut regions before the cutting process. This protective layer acts as a cushion that prevents cracks from propagating through the gate stack during the word line cutting process. The protective layer is subsequently removed or sacrificed, having fulfilled its protective function, thereby preventing reliability issues while allowing necessary connectivity improvements.
3Reliability
If additional processes are added to prevent crack defects, then reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the protective layer formation with existing manufacturing processes, such as integrating it with the gate stack formation or interlayer dielectric deposition steps. Rather than adding a separate dedicated protective step, the protective function is merged into a process that is already required for other structural reasons, thereby preventing cracks without significantly increasing manufacturing complexity or process steps.
Data Source
AI summary
The present disclosure provides for apparatuses and systems including integrated circuit devices. In some embodiments, an integrated circuit device includes a semiconductor substrate including a memory cell area and a connection area, a gate stack including a plurality of word line gate layers and a plurality of insulating layers and having a step structure in the connection area, a word line cut region passing through the plurality of word line gate layers in the memory cell area and the connection area and extending in a third direction, a plurality of first channel structures disposed on the memory cell area, a string select line gate layer disposed on the gate stack in the memory cell area, a plurality of second channel structures passing through the string select line gate layer, and a string select line cut region passing through the string select line gate layer.