Vertical Memristor With Stacked 2D Materials
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Solution Overview
Problem
Current memristor technologies face challenges in achieving high integration density and low-power characteristics with random access memory cells, particularly in neuromorphic computing platforms, where efficient resistance switching and stable operation across varying resistance states are essential.
Innovation Solution
The development of vertical memristors with a resistance change layer composed of stacked two-dimensional material layers, including defective grain boundaries, which form conductive filaments in response to electrical signals, enabling bipolar resistive switching and stable operation within a specific voltage range, thereby enhancing integration density and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memristor structures are used, then device complexity is reduced, but integration density and power characteristics deteriorate
Solution Approach 1:
The patent transitions from planar horizontal memristor structures to vertical three-dimensional structures. The resistance change layer is stacked vertically between upper and lower electrodes, enabling higher integration density by utilizing the vertical dimension for cell stacking and three-dimensional NAND integration in neuromorphic computing platforms.
Solution Approach 2:
The resistance change layer employs composite two-dimensional material structures, specifically stacked layers of different two-dimensional materials (such as MoS2, WS2, MoSe2, WSe2, or other transition metal dichalcogenides) with defective grain boundaries. This composite structure enables both high integration density and low-power characteristics through controlled conductive filament formation.
2Productivity
If higher resistance switching efficiency is achieved, then power consumption increases, but low-power characteristics deteriorate
Solution Approach 1:
The patent utilizes controlled changes in material parameters through defective grain boundaries in two-dimensional materials. The defects serve as nucleation sites for conductive filament formation, enabling resistance switching at lower voltages (0.1-0.5V) while maintaining efficient switching characteristics. The ohmic conduction slope is maintained within 0.8-1.2 for stable operation.
Solution Approach 2:
Defective grain boundaries act as intermediaries that facilitate controlled ion migration and conductive filament formation. The line-type and dot-type defects in the two-dimensional material layers provide preferential pathways for filament growth, enabling efficient resistance switching at low power consumption by mediating the interaction between applied voltage and material response.
3Reliability
If stable operation across resistance states is achieved, then device complexity increases, but manufacturing complexity worsens
Solution Approach 1:
The patent introduces localized defects (line-type and dot-type) within the two-dimensional material layers at specific grain boundary regions. These localized quality variations create controlled nucleation sites for conductive filament formation, ensuring stable and reproducible resistance switching behavior without requiring complex manufacturing processes. The defects are confined to specific locations rather than distributed uniformly.
Solution Approach 2:
Instead of attempting to create perfectly crystalline two-dimensional material layers, the patent inverts the approach by intentionally incorporating controlled defects and grain boundaries. These normally considered imperfections are strategically used to enhance reliability by providing consistent filament formation pathways, simplifying manufacturing while improving operational stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for efficient bipolar resistive switching and stable operation across high and low resistance states, facilitating high integration density and low-power neuromorphic computing, while maintaining stability and efficiency in neuromorphic devices.
Implementation Method 1
the resistance change layer may be configured to form a conductive filament on the defective grain boundaries in response to an application of an electrical signal to the lower electrode and the upper electrode
Implementation Method 2
the memristor may be configured to perform a bipolar resistive switching operation
Implementation Method 3
the resistance change layer may have resistance characteristics that vary in an analog manner according to a sweep of an applied electrical signal
Implementation Method 4
in the memristor after undergoing a forming operation, an ohmic conduction slope of the memristor in a high resistance state may be constant and an ohmic conduction slope of the memristor in a low resistance state may be constant
Data Source
AI summary
Provided are memristors and neuromorphic devices including the memristors. A memristor includes a lower electrode and an upper electrode that are apart from each other and first and second two-dimensional material layers that are arranged between the lower electrode and the upper electrode and stacked without a chemical bond therebetween.