Vertical MEMS-ASIC Integration on Single Substrate
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Solution Overview
Problem
The manufacturing of semiconductor devices with both MEMS structures and ASIC electronic circuits using CMOS techniques is challenging due to incompatibility in processing conditions, leading to large device dimensions and reliability issues, particularly in portable or wearable applications where compactness is desired.
Innovation Solution
Integrating MEMS and ASIC electronic circuits in the same processed substrate, with vertically opposite surfaces and forming interconnection structures through the substrate to maintain separate manufacturing processes, allowing standard CMOS or HCMOS techniques without affecting each other's integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MEMS and ASIC are manufactured separately in respective substrates and bonded together, then manufacturing compatibility is maintained, but device dimensions become large and reliability decreases
Solution Approach 1:
The patent merges the MEMS structure and ASIC electronic circuit into a single integrated substrate, eliminating the need for separate substrate manufacturing and bonding operations. This integration maintains manufacturing compatibility while significantly reducing device dimensions by consolidating previously separate components into one unified structure.
Solution Approach 2:
The patent utilizes vertical stacking architecture where MEMS structures are formed on upper layers and ASIC circuits on lower layers of the same substrate. This three-dimensional integration approach reduces the horizontal footprint of the device while maintaining functional separation, effectively addressing the volume reduction requirement without compromising manufacturing compatibility.
2Ease of manufacture
If MEMS and ASIC are manufactured separately and bonded together, then manufacturing compatibility is maintained, but reliability of electrical connections deteriorates
Solution Approach 1:
By integrating MEMS and ASIC in the same substrate with direct planar connections at the front-end level, the patent eliminates intermediate bonding interfaces and wire bonds that were sources of reliability issues. The merged structure provides direct electrical pathways with fewer potential failure points, improving connection reliability while maintaining manufacturing compatibility.
3Device complexity
If standard CMOS techniques are used for both MEMS and ASIC, then manufacturing simplicity is maintained, but processing condition incompatibility arises
Solution Approach 1:
The patent applies local quality by implementing process-specific zones within the same substrate - dedicated regions optimized for MEMS processing (higher temperatures, specific materials) and other regions for ASIC CMOS processing (lower temperatures, standard metallization). This allows standard CMOS techniques to be used for ASIC while accommodating MEMS-specific requirements in localized areas, maintaining manufacturing simplicity despite processing incompatibilities.
Solution Approach 2:
The manufacturing process is segmented into separate process streams that converge on the same substrate. MEMS structures are fabricated using high-temperature epitaxial deposition and specific release processes in designated areas, while ASIC circuits are processed using standard CMOS steps in other areas. This segmentation allows each technology to use its optimal process conditions without compromising the other, reducing overall device complexity.
4Ease of manufacture
If separate substrate bonding is used to integrate MEMS and ASIC, then manufacturing feasibility is maintained, but parasitic components and noise increase
Solution Approach 1:
The integration of MEMS and ASIC in a single substrate with direct planar interconnections eliminates the need for separate substrate bonding, wire bonding, and complex interconnection structures. This merging reduces the length and complexity of electrical pathways, thereby minimizing parasitic inductance, capacitance, and resistance, and reducing noise coupling between the two functional blocks while maintaining manufacturing feasibility.
Data Source
Figure 1~2
Figure 3A~3C
Figure 3D~3E
AI summary
A process for manufacturing an integrated semiconductor device (55), envisages: forming a MEMS structure (26); forming an ASIC electronic circuit (36); and electrically coupling the MEMS structure to the ASIC electronic circuit (36). The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate (20) including semiconductor material; wherein the MEMS structure (26) is formed at a first surface (20a) of the substrate, and the ASIC electronic circuit is formed at a second surface (20b') of the substrate (20), vertically opposite to the first surface (20a) in a direction transverse to a horizontal plane of extension of the first surface (20a) and of the second surface (20b').