Vertical Metal Resistor Structure for Semiconductor Area Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling down while maintaining efficient resistance values and reducing fabrication costs, as traditional resistor structures occupy large horizontal areas and increase vertical height, leading to inefficiencies and increased costs.
Innovation Solution
A semiconductor device with a self-aligned vertical metal resistor structure between gate spacers, where the metal resistor is formed at the same height as the gate spacers, reducing horizontal area and allowing for precise resistance tuning through adjustable insulating liner thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional resistor structures are used, then resistance values can be achieved, but horizontal area occupied is large and vertical height increases
Solution Approach 1:
The patent transitions the resistor structure from a horizontal planar configuration to a vertical three-dimensional configuration. The metal resistor is formed between gate spacers in the vertical direction, utilizing the third dimension (height) to achieve the required resistance value while minimizing horizontal footprint. This dimensional transformation directly resolves the contradiction by maintaining resistance functionality while dramatically reducing the horizontal area occupied.
Solution Approach 2:
The metal resistor structure is nested within the vertical space defined by the gate spacers, utilizing the existing vertical architecture of the semiconductor device. The resistor is integrated into the vertical columnar region between spacers, effectively nesting the resistive element within the device's three-dimensional structure rather than occupying additional horizontal space.
2Manufacturing precision
If traditional resistor structures are used, then resistance values can be achieved, but vertical height increases
Solution Approach 1:
The patent utilizes the vertical dimension as the primary direction for resistor formation, confining the resistive structure within the vertical space between gate spacers. This approach achieves the required resistance through controlled metal filling in the vertical direction while maintaining a compact overall height that is consistent with the gate spacer dimensions, rather than adding excessive vertical height.
3Area of stationary object
If horizontal area is reduced, then space utilization improves, but resistance tuning precision may be affected
Solution Approach 1:
The patent enables resistance tuning by varying multiple parameters of the vertical metal resistor structure, including the thickness, width, and height of the metal filling, as well as the thickness of the insulating liner. These parameter changes allow precise control of resistance values while maintaining a compact horizontal footprint, as the tuning is achieved through dimensional adjustments in the vertical configuration rather than horizontal expansion.
Solution Approach 2:
The insulating liner acts as an intermediary element between the metal resistor and the source/drain region, enabling precise control of the resistor geometry and electrical characteristics. The liner thickness can be independently controlled to adjust the effective resistive path while maintaining the compact vertical structure, providing an additional degree of freedom for resistance tuning without increasing horizontal area.
Data Source
AI summary
A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.