Vertical MIM Capacitor-Avalanche Diode Layout for Compact ESD Protection
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Solution Overview
Problem
The increasing demand for miniaturization of power amplifier integrated circuits (PAICs) due to advancements in 5G cellular networks and MIMO systems has led to a space-dominant issue with ESD protection structures, which occupy a significant fraction of the IC floor space, particularly in small cell, lower power applications, and do not efficiently utilize available space.
Innovation Solution
The integration of vertically-integrated capacitor-avalanche diode structures, where a Metal-Insulator-Metal (MIM) capacitor is formed over an avalanche diode (AD) in a metal layer system on a semiconductor substrate, allowing for compact ESD protection and capacitance in a three-dimensional space, enabling efficient use of IC floor space and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection structures are integrated into PAIC die topologies, then ESD protection capability is improved, but IC floor space is consumed
Solution Approach 1:
The patent combines the ESD protection structure and capacitor into a single integrated unit sharing common elements (metal layers, substrate regions). The ESD protection structure includes a first metal layer patterned to form electrodes, and the capacitor shares this metal layer system, allowing both functions to coexist in a reduced footprint while maintaining ESD protection capability
Solution Approach 2:
The metal layer system serves multiple functions: it forms the ESD protection structure (avalanche diode with cathode and anode regions), creates the capacitor electrodes, and provides interconnect functionality. This multi-functional design allows a single structure to provide both ESD protection and capacitance, reducing the total space required
2Area of stationary object
If PAIC die dimensions are reduced for miniaturization, then device size is reduced, but ESD protection structures become space-dominant
Solution Approach 1:
The capacitor is nested within the ESD protection structure footprint. The capacitor's first electrode is formed using the same metal layer that defines the ESD protection structure, allowing the capacitor to occupy the same planar space without increasing the overall device footprint. This nesting enables miniaturization while maintaining adequate ESD protection
3Reliability
If traditional lateral ESD protection structures are used, then ESD protection is provided, but parasitic capacitances are increased
Solution Approach 1:
The patent transitions from traditional lateral ESD protection structures to a vertically-integrated design where the avalanche diode and capacitor are stacked in the vertical dimension rather than arranged laterally. The avalanche diode cathode region contacts the substrate, and the capacitor electrodes extend vertically, reducing the lateral footprint and associated parasitic capacitances while maintaining ESD protection functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a compact footprint for PAICs, allowing for reduced overall size and cost, while maintaining or improving ESD protection capabilities, and enabling additional circuit elements or increased dimensions of existing components, with benefits including reduced current leakage and design flexibility.
Implementation Method 1
an avalanche diode (AD) element or device... electrically coupled in parallel with the MIM capacitor... allowing for compact ESD protection
Implementation Method 2
Metal-Insulator-Metal (MIM) capacitor is formed over an avalanche diode (AD)
Data Source
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AI summary
Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.