Vertical MIM Capacitor Structure for InFO Package
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Solution Overview
Problem
Conventional metal-insulator-metal (MIM) capacitors in integrated circuits face challenges in controlling inter-metal layer thickness, leading to high variation in capacitance, which complicates the production of capacitors with target values.
Innovation Solution
The implementation of a semiconductor structure with vertical capacitors, where interlaced vertical conductive structures are used with a dielectric material filled between them, integrated into an Integrated Fan-Out (InFO) package, allowing for precise control of capacitance through the use of high-k dielectric materials and careful manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional horizontal MIM capacitor structures are used, then chip area utilization is improved, but manufacturing precision of capacitance values deteriorates due to difficulty in controlling inter-metal layer thickness
Solution Approach 1:
The patent transitions from conventional horizontal MIM capacitor structures to vertical MIM capacitor structures. This dimensional change allows the capacitor to extend in the vertical direction (through the interlayer dielectric) rather than only in the horizontal plane, enabling better control of capacitance through vertical electrode structure design while maintaining compact horizontal footprint.
Solution Approach 2:
The patent changes the structural parameters of the MIM capacitor by forming vertical electrodes that extend through the interlayer dielectric, rather than using horizontal stacked metal layers. This parameter change enables capacitance control through electrode height, width, and spacing rather than through difficult-to-control inter-metal layer thickness.
2Quantity of substance
If inter-metal layer thickness is reduced to increase capacitance, then capacitance value is improved, but manufacturing precision deteriorates due to difficulty in controlling thin layer thickness
Solution Approach 1:
The patent moves from controlling capacitance through horizontal inter-metal layer thickness to controlling capacitance through vertical electrode dimensions. The vertical electrodes extend through the interlayer dielectric, allowing capacitance to be adjusted by changing electrode height, width, or spacing rather than by controlling difficult-to-manufacture thin metal layer thickness.
3Quantity of substance
If capacitor area is increased to increase capacitance, then capacitance value is improved, but chip area requirement worsens
Solution Approach 1:
The patent utilizes the vertical dimension by forming electrodes that extend through the interlayer dielectric in the vertical direction. This allows the capacitor to achieve higher capacitance values by increasing vertical electrode height or density rather than by expanding horizontal chip area, effectively using the third dimension for capacitance scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more consistent and controlled capacitance values, reducing variations and improving the manufacturing efficiency of MIM capacitors, while also allowing for a more compact chip design by utilizing vertical structures within the InFO package.
Implementation Method 1
a dielectric material 160 is filled between the electrode 120 and the electrode 140 to form an insulating structure
Data Source
AI summary
A method of forming a semiconductor device includes forming a first redistribution line on a substrate; forming a plurality of first vertical conductive structures on the first redistribution line and electrically coupled to the first redistribution line; forming a plurality of second vertical conductive structures on the substrate, wherein the first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and the second vertical conductive structures are spaced apart from the first redistribution line; attaching a device die on the substrate; applying a molding compound in a molding layer overlying the substrate to surround the device die; and forming a second redistribution line on the molding layer, wherein the second redistribution line is electrically coupled to the second vertical conductive structures.