Interleaved Vertical MIM Capacitor Structure for Higher Capacitance
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Solution Overview
Problem
Existing MIM capacitors in integrated circuits face challenges with high manufacturing costs and space occupancy due to the need for high aspect ratio trenches, uniform electrode and insulator deposition, and additional through vias, which affect capacitance and efficiency.
Innovation Solution
A vertically stacked multi-layer MIM capacitor design with interleaved electrodes is introduced, eliminating the need for high aspect ratio trenches and additional through vias, and utilizing a sacrificial multi-layer stack to form capacitor electrodes and dielectric layers, enhancing capacitance through increased overlap area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high aspect ratio trenches are used to increase capacitance, then capacitance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from planar capacitor structures to vertically stacked multi-layer structures, utilizing the third dimension (height) to increase capacitance. By stacking multiple capacitor layers vertically, the effective capacitance area is increased without requiring high aspect ratio trenches, thus resolving the contradiction between capacitance improvement and manufacturing complexity.
Solution Approach 2:
The patent employs nested capacitor structures where multiple capacitor layers are stacked within a compact vertical space. Each capacitor layer is nested within the structure, with alternating electrode and dielectric layers forming a compact nested arrangement that maximizes capacitance within a small footprint while avoiding complex high aspect ratio trench formation.
2Quantity of substance
If additional through vias are added to improve capacitance, then capacitance is improved, but space occupancy and manufacturing cost increase
Solution Approach 1:
Instead of adding more through vias in the planar direction (increasing space occupancy), the patent utilizes the vertical dimension by stacking multiple capacitor layers. This approach increases capacitance by exploiting the third dimension rather than expanding the horizontal footprint, thus resolving the contradiction between capacitance improvement and space occupancy.
Solution Approach 2:
The patent merges multiple capacitor functions into a single vertically stacked structure. By combining multiple capacitor layers into one integrated stack, the design achieves increased capacitance without requiring separate through vias for each capacitor, thereby reducing space occupancy and manufacturing complexity.
3Quantity of substance
If uniform electrode and insulator deposition is required for high aspect ratio trenches, then capacitance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent avoids the deposition challenges of high aspect ratio trenches by transitioning to a vertically stacked structure where electrodes and dielectrics are deposited in alternating horizontal layers. This approach eliminates the need for precise uniform deposition into deep vertical trenches, as the deposition surfaces are more accessible and easier to control, thus resolving the contradiction between capacitance improvement and manufacturing precision requirements.
Data Source
AI summary
An integrated circuit structure includes a first capacitor electrode, a second capacitor electrode, and a first insulator. The first capacitor electrode includes a first vertical portion on a substrate and a plurality of first lateral portions laterally extending from the first vertical portion and arranged along a direction perpendicular to a top surface of the substrate. The second capacitor electrode spaced apart from the first capacitor electrode. The second capacitor includes a second vertical portion on the substrate and a plurality of second lateral portions laterally extending from the second vertical portion and arranged along the direction perpendicular to the top surface of the substrate. The first lateral portions of the first capacitor electrode interleave with the second lateral portions of the second capacitor electrode. The first insulator interposes the first capacitor electrode and the second capacitor electrode.