Vertical MISFET SRAM Cell Layout for Leakage Reduction
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Solution Overview
Problem
The miniaturization of SRAMs using vertical MISFETs faces challenges due to increased leakage current and variation in characteristics, making it difficult to further reduce size and improve integration density, as well as issues with connecting underside source/drain to wiring without extra area requirements and high wiring resistance.
Innovation Solution
A semiconductor storage device with a specific arrangement of transistors and local interconnects that eliminates the need for contact plugs and allows high-resistance wiring, enabling efficient connection of underside source/drain to upper-layer wiring while maintaining a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical MISFETs are used to improve integration density, then the occupied area on the substrate is reduced, but leakage current increases and characteristic variation worsens
Solution Approach 1:
The patent transitions from planar MISFETs to vertical MISFETs, changing the current flow direction from horizontal (in-plane) to vertical (perpendicular to substrate). This dimensional change reduces the occupied area on the substrate while maintaining transistor functionality, directly addressing the integration density improvement goal.
Solution Approach 2:
The patent modifies key geometric parameters of the MISFET structure, including gate length (L), gate width (W), and channel thickness (Tch), to optimize performance. By carefully controlling these parameters in the vertical configuration, the patent aims to reduce leakage current and minimize characteristic variation while maintaining the area reduction benefits.
2Reliability
If contact plug is added to connect underside source/drain to wiring, then electrical connection is achieved, but the advantage of small occupied area is impaired
Solution Approach 1:
The patent merges the source/drain extension function with the contact plug function into a single integrated structure. The source/drain region extends laterally from beneath the column portion and directly connects to the upper-layer wiring, eliminating the need for a separate contact plug and reducing the occupied area.
Solution Approach 2:
Instead of connecting to the underside source/drain from below through a contact plug (conventional approach), the patent inverts the connection approach by having the source/drain region extend upward and laterally to meet the wiring from the side, thereby eliminating the need for a downward-contact structure.
3Area of stationary object
If wiring is formed under the column portion to avoid extra area, then area is saved, but wiring resistance increases due to heat-resistant material requirements
Solution Approach 1:
The patent changes the wiring arrangement from a two-dimensional planar layout to a three-dimensional stacked configuration. By forming wiring layers above the column portion at different heights, the patent achieves both area savings and maintains low wiring resistance through direct vertical connections.
Solution Approach 2:
The patent introduces an intermediary connection structure that bridges the underside source/drain and the upper-layer wiring. This intermediary structure allows the use of low-resistance materials in the wiring while maintaining electrical connection to the heat-sensitive underside source/drain region.
4Reliability
If complex lamination steps and high-temperature processing are used to form wiring under MISFET, then wiring connection is achieved, then manufacturing complexity and processing difficulty increase
Solution Approach 1:
The patent performs preliminary actions by forming the source/drain regions with lateral extensions before forming the upper-layer wiring. This preliminary configuration of the source/drain structures enables direct connection to the wiring in subsequent steps, eliminating the need for complex lamination and high-temperature processing that would otherwise be required.
Solution Approach 2:
The patent inverts the conventional manufacturing sequence by first forming the active transistor structures with integrated connection paths, then forming the wiring layers above. This inverted approach eliminates the need for subsequent complex steps to connect wiring to underside source/drain regions, simplifying the overall manufacturing process.
Data Source
AI summary
An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other.