Vertical MOS Transistor Layout for Compact Dual Current Paths
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Solution Overview
Problem
There is a demand for downsizing circuits that include at least one vertical MOS transistor.
Innovation Solution
A semiconductor device with a dual configuration of two vertical MOS transistors, where the transistors are arranged in non-overlapping regions on a semiconductor substrate, with a common drain region and specific pad placements, allowing integration of two paths with different current values into one conductive path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two separate MOS transistors are used to handle different current paths, then the circuit can support multiple current values, but the circuit area increases
Solution Approach 1:
The patent combines two separate MOS transistor structures into a single integrated device with a shared substrate. The first and second MOS transistors are formed on the same semiconductor substrate with shared regions (first substrate region and second substrate region), allowing multiple current paths to be handled within a single compact structure rather than requiring separate discrete transistors.
Solution Approach 2:
The patent utilizes vertical channel structures extending through the substrate thickness dimension, transitioning from planar 2D transistor layouts to 3D vertical configurations. This dimensional change allows multiple transistor functions to be stacked and integrated within a smaller footprint area while maintaining distinct current paths through different vertical regions.
2Device complexity
If MOS transistors are integrated into a single substrate, then the device complexity decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the semiconductor substrate into distinct functional regions (first substrate region, second substrate region, third substrate region) with clearly defined boundaries and non-overlapping lateral extents. This segmentation approach allows each region to be independently formed and controlled during manufacturing, reducing the precision requirements compared to fully overlapping complex structures while maintaining integration benefits.
Solution Approach 2:
The patent applies different doping concentrations and material properties to specific regions (higher doping in contact regions, lower doping in channel regions) to optimize local electrical characteristics. This localized property differentiation enables precise control of current paths and electrical behavior in each region without requiring ultra-precise global alignment, as each region can be independently tailored.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer that includes a semiconductor substrate on a back face side and is divided into a first region, a second region, and a third region that do not overlap each other and are not dispersedly disposed in a plan view of the semiconductor device; a first vertical metal-oxide-semiconductor (MOS) transistor provided in the first region of the semiconductor layer; a second vertical MOS transistor provided in the second region of the semiconductor layer; and a drain pad connected to the semiconductor substrate, at a position within the third region in the plan view of the semiconductor device. In the plan view of the semiconductor device, the third region is interposed between the first region and the second region. In the plan view of the semiconductor device, an area of the first region is larger than an area of the second region.