Vertical MOS Transistor Layout for Dual Current Paths
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Solution Overview
Problem
In a vertical MOS transistor with a dual configuration, providing an ancillary pathway in a limited device area can impede the original conduction of charging and discharging currents.
Innovation Solution
A facedown mountable, chip-size-package type semiconductor device with a semiconductor substrate, low-concentration impurity layer, and two vertical MOS transistors, where the transistors are arranged in a rectangular semiconductor layer with a common drain region, allowing for a secondary pathway to pass a relatively small current without interrupting the primary pathway that passes a large current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an ancillary pathway is provided in a vertical MOS transistor with dual configuration, then the battery protection circuit can handle overcharge/overdischarge conditions, but the conduction resistance of the primary charging/discharging pathway increases
Solution Approach 1:
The semiconductor layer is divided into distinct first and second regions, each hosting separate vertical MOS transistors. The first region handles primary charging/discharging operations while the second region provides ancillary protection functions. This spatial segmentation allows independent optimization of conduction paths, enabling the primary pathway to maintain low resistance while the ancillary pathway provides protection without interfering with normal operation.
2Area of stationary object
If the device area is limited, then the chip size is reduced, but it becomes difficult to provide both primary and ancillary pathways without interference
Solution Approach 1:
The patent combines multiple functions into a single integrated semiconductor device structure. Both the primary vertical MOS transistor (for charging/discharging) and the ancillary vertical MOS transistor (for protection) are merged within the same semiconductor layer, sharing common elements such as the semiconductor substrate and low-concentration impurity layer. This merging approach achieves dual pathway functionality while minimizing the overall device area, as the transistors can share infrastructure rather than requiring completely separate structures.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional arrangement of transistor components within the semiconductor layer. By arranging the first and second regions adjacently in the planar dimension while extending structures vertically into the semiconductor substrate, the design achieves high functional density without proportionally increasing the planar device area. This dimensional optimization allows both primary and ancillary pathways to coexist in a compact footprint.
Data Source
AI summary
A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.