Vertical MOS Transistor Electrode Layout for CSP Reliability
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Solution Overview
Problem
Conventional CSP semiconductor devices face challenges in electrical characteristics and mounting reliability due to high connection resistance and the risk of short-circuits between electrodes.
Innovation Solution
A semiconductor device with a configuration of vertical metal oxide semiconductor transistors, where the closest points between source and gate electrodes are inclined relative to the chip side, increasing electrode distance and area, thereby reducing connection resistance and preventing short-circuits, while also optimizing electrode width and arrangement for improved solder bonding and reduced void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrode area is increased to reduce connection resistance, then electrical characteristics are improved, but the risk of short-circuit between electrodes increases
Solution Approach 1:
The patent applies asymmetry by arranging electrodes in a non-symmetric pattern where source electrodes are positioned at corners and midpoints of sides, while gate electrodes are offset from the center. This asymmetric layout increases the minimum distance between electrodes of different potentials, reducing short-circuit risk while maintaining adequate electrode area for low connection resistance.
Solution Approach 2:
The patent utilizes two-dimensional space optimization by strategically positioning electrodes at corner and side midpoint locations rather than uniform distribution. This dimensional arrangement maximizes the minimum inter-electrode distance across the electrode plane, effectively reducing short-circuit risk while preserving sufficient electrode area.
2Reliability
If electrode area is increased to reduce connection resistance, then connection resistance is reduced, but electrode spacing must be maintained to prevent short-circuits
Solution Approach 1:
The patent segments the electrode arrangement into distinct functional zones: corner electrodes (source), side midpoint electrodes (source), and centrally positioned gate electrodes. This segmentation allows each electrode type to be optimally positioned for its function while maintaining adequate spacing, achieving both low connection resistance and short-circuit prevention.
Solution Approach 2:
The patent optimizes two-dimensional electrode layout by placing source electrodes at corner and side midpoint positions, creating maximum separation from gate electrodes in the central region. This dimensional arrangement increases the minimum spacing between electrodes of different potentials while maintaining adequate electrode area for low connection resistance.
3Ease of manufacture
If conventional electrode arrangement is used, then manufacturing is simple, but mounting reliability is insufficient
Solution Approach 1:
The patent implements an asymmetric electrode arrangement that, while slightly more complex than conventional symmetric layouts, significantly improves mounting reliability. The asymmetric positioning of source electrodes at corners and side midpoints, combined with offset gate electrode positions, creates optimal spacing that prevents short-circuits during mounting operations.
Solution Approach 2:
The patent segments the electrode layout into distinct functional groups (corner sources, side midpoint sources, central gates) that can be manufactured using standard photolithography processes. This segmented arrangement maintains manufacturing simplicity while achieving superior mounting reliability through optimized inter-electrode spacing.
Data Source
AI summary
A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.