Vertical MOS Transistor Layout for Uniform Heat in Common-Drain Packages
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Solution Overview
Problem
Semiconductor devices with multiple vertical MOS transistors sharing a common drain region face issues with localized heat generation, particularly when transistors have different maximum specified currents, leading to uneven conduction resistance and heat distribution.
Innovation Solution
The semiconductor device design includes N vertical MOS transistors with a common drain region, where the surface area of each transistor increases with its maximum specified current, reducing conduction resistance and inhibiting localized heat generation by proportionally increasing the surface area with the square of the current, thus maintaining equal heat generation across transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple vertical MOS transistors share a common drain region with equal surface areas, then device complexity is reduced and manufacturing is simplified, but localized heat generation occurs due to uneven conduction resistance when transistors have different maximum specified currents
Solution Approach 1:
The patent applies local quality by making the surface area of each vertical MOS transistor proportional to the square of its maximum specified current. This means transistors with different current ratings have different surface areas, creating non-uniform local properties that compensate for the uneven heat generation caused by different conduction resistances. The larger current transistors have larger surface areas, which reduces their conduction resistance and balances the heat generation across all transistors sharing the common drain region.
2Temperature
If transistor surface area is increased proportionally to the square of maximum specified current, then conduction resistance is reduced and heat generation is equalized, but device area increases
Solution Approach 1:
The patent applies parameter changes by modifying the surface area parameter of each transistor based on its maximum specified current. Specifically, the surface area is set proportional to the square of the maximum current, which changes the physical dimension parameter to achieve the desired electrical characteristic balance. This parameter adjustment equalizes the heat generation across transistors while optimizing the overall device area for the given current requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces localized heat generation by inversely proportional conduction resistance to the square of the maximum specified current, ensuring uniform heat distribution and reducing the size of the semiconductor device by using appropriately sized transistors.
Implementation Method 1
The semiconductor substrate functions as a common drain region for the N vertical MOS transistors
Implementation Method 2
the surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor
Data Source
AI summary
A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.