Vertical MOS Memory Cell Structure for Stable Data Retention
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Solution Overview
Problem
Current memory devices using semiconductor elements face challenges in achieving high packaging density, accuracy, and reduced cost without relying on variable resistance elements or capacitors, particularly in maintaining data retention and correcting fluctuations in floating body channel voltage.
Innovation Solution
A memory device design featuring a MOS transistor structure with a concave-shaped vertical second semiconductor region, specific impurity regions, and gate insulating and conductor layers, allowing for controlled voltage applications to manage carrier generation and retention, thereby enhancing data writing and erasure operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar MOS transistor is used, then the structure is simple and manufacturing is easier, but packaging density is low
Solution Approach 1:
The patent transitions from a planar two-dimensional transistor structure to a three-dimensional vertical structure by forming a columnar semiconductor region extending in the vertical direction. The gate electrode surrounds the channel-forming region in a circumferential manner, creating a vertical channel that extends from the first surface to the second surface of the semiconductor substrate. This dimensional change enables significantly higher packaging density while maintaining manufacturing feasibility through established semiconductor processing techniques.
2Device complexity
If capacitorless DRAM is used, then device complexity is reduced, but data retention characteristics deteriorate due to floating body voltage fluctuations
Solution Approach 1:
The patent extracts the problematic floating body effect by forming a pinned body structure where the columnar semiconductor region is electrically connected to a fixed potential (either ground or power supply) through dedicated connection structures. This extraction of the floating body eliminates voltage fluctuations and carrier accumulation issues while maintaining the simplified capacitorless memory cell structure, thereby improving data retention characteristics without increasing device complexity.
Solution Approach 2:
The patent introduces intermediary connection structures that electrically connect the columnar semiconductor region to fixed potential references. These intermediary structures act as mediators to stabilize the body potential, preventing unwanted voltage fluctuations and carrier accumulation that would otherwise degrade data retention. The intermediary connections enable reliable operation while maintaining the simple capacitorless architecture.
3Area of stationary object
If SGT is used, then packaging density increases, but manufacturing precision requirements increase due to vertical channel formation
Solution Approach 1:
The patent applies preliminary action by first forming the columnar semiconductor region with the desired vertical geometry before proceeding to gate electrode formation and channel creation. The vertical channel structure is established through pre-defined mask patterns and etch processes that create the columnar region, ensuring precise vertical alignment. This preliminary formation of the vertical structure simplifies subsequent processing steps and maintains manufacturing precision while achieving high packaging density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases packaging density, improves data retention, and reduces power consumption by effectively managing carrier concentrations and leakage currents, resulting in a higher-density and more efficient memory cell array.
Implementation Method 1
out of positive hole groups and electron groups generated in a channel by impact ionization phenomenon using a source-drain current
Implementation Method 2
a first gate insulating layer covering part of the second semiconductor region; a first gate conductor layer placed in contact with the first gate insulating layer
Implementation Method 3
a second semiconductor region extending in a vertical direction by being placed in contact with the first impurity region, with a surface of the second semiconductor region being concave in vertical section
Data Source
AI summary
In a semiconductor memory device, an n-type semiconductor layer is formed on a p-type semiconductor region on a substrate, a p-type first semiconductor layer having a columnar shape and concave top surface extends vertically from part of the n-type semiconductor layer, the p-type first semiconductor layer and n-type semiconductor layer are partially covered with an insulating layer, a first gate insulating layer is placed in contact with the p-type first semiconductor layer, a first gate conductor layer is placed in contact with the first gate insulating layer, and a second gate insulating layer, a second gate conductor layer, and an access transistor with an n+ layer provided on both sides are installed along a surface of the p-type first semiconductor layer.