Vertical MOS Transistor Asymmetrical Doping High Voltage
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Solution Overview
Problem
High voltage semiconductor devices face challenges in maintaining high withstand voltage while minimizing device size and simplifying manufacturing processes, as existing technologies require complex processing steps and can lead to low yield and increased risk of voltage leakage.
Innovation Solution
A semiconductor device configuration featuring a specific arrangement of insulating and conductive films, impurity diffusion areas, and silicide layers, where the third impurity diffusion area functions as an electrical field buffering area adjacent to the fourth impurity diffusion area, allowing for high voltage performance without increasing device size, and a manufacturing method that simplifies processing by forming conductive films perpendicular to the substrate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long gate length is used to secure withstand voltage, then the withstand voltage is improved, but the device size increases
Solution Approach 1:
The patent transitions from a planar gate structure to a vertical gate structure extending in the depth direction. The gate electrode penetrates through the insulating film from the top surface to the bottom, creating a three-dimensional configuration that increases the effective gate length without expanding the planar device footprint, thus achieving high withstand voltage with compact size.
Solution Approach 2:
The patent embeds the gate electrode within the insulating film structure, with the gate penetrating through the insulating film and positioned adjacent to impurity diffusion areas. This nested configuration allows the gate to interact with multiple regions (top and bottom surfaces) simultaneously, effectively increasing the gate length while maintaining a compact overall structure.
2Reliability
If ion implantation is used to form electrical field buffering area, then the withstand voltage is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of the electrical field buffering area with the gate electrode structure. The impurity diffusion areas are positioned to overlap with the gate electrode region, allowing a single ion implantation process to achieve both the buffering function and the gate doping, thereby reducing manufacturing steps and complexity.
Solution Approach 2:
The gate electrode region serves multiple functions: it provides the primary gate control function, acts as an electrical field buffering area through impurity diffusion, and influences the channel formation. This multi-functionality reduces the need for separate structures and processes, simplifying the overall manufacturing while maintaining high withstand voltage.
3Area of stationary object
If the channel area is formed lower than the element isolation insulating film, then the device size is reduced, but the electrical field buffering effect decreases and leak risk increases
Solution Approach 1:
The patent positions the channel area and impurity diffusion regions in the depth direction adjacent to the vertical gate electrode, rather than solely in the planar direction. This three-dimensional arrangement ensures that the channel area remains within the effective electric field buffering zone provided by the gate structure, maintaining high withstand voltage and low leak risk while keeping the planar device size compact.
4Reliability
If the gate electrode has a step structure, then the electrical field buffering is improved, but the manufacturing precision requirement increases and yield decreases
Solution Approach 1:
The patent employs an asymmetrical impurity diffusion profile with different doping concentrations at different depths and positions relative to the gate electrode. This asymmetrical doping creates effective electrical field buffering without requiring a stepped gate structure, thereby avoiding the high precision processing and low yield issues associated with step formation while maintaining superior electric field control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high withstand voltage with reduced device size and improved manufacturing yield by providing effective electrical field buffering and reducing contact resistance, allowing for the production of high-performance MOS transistors with simplified processing steps.
Implementation Method 1
a source diffusion area 102 and a drain diffusion area 103 are formed through ion implantation of a P-type high concentration impurity
Data Source
AI summary
A semiconductor device comprises a first conductive film formed downward, perpendicular to a substrate, penetrating through a first insulating film, a second conductive film formed downward along an outer wall of a second insulating film, a third insulating film formed from the bottom of the second conductive film to the top of the substrate in an area sandwiched between the first and second insulating films, contacting with at least the bottom of the second conductive film and an outer wall on a side which does not contact with the second insulating film, and a first impurity diffusion area of a first conductivity type, a second impurity diffusion area of a second conductivity type, a third impurity diffusion area of the first conductivity type and a fourth impurity diffusion area of the first conductivity type in a high concentration layered within the area sandwiched between the first and third insulating films.