Vertical MOS Transistor Fabrication with Etch-Protection Sidewall
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Solution Overview
Problem
The existing methods for fabricating vertical MOS transistors face challenges such as the prevention of electrical contact due to the presence of bottom oxide, which can damage the gate oxide during etching, and contamination risks from etching chemicals, along with limitations in accessing and refilling small holes.
Innovation Solution
A method involving forming a conductive layer in a dielectric layer, etching a hole to expose the inner lateral edge, creating a gate oxide and bottom oxide, and using an etch-protection sidewall to protect the gate oxide while etching the bottom oxide, allowing semiconductor material deposition and dopant diffusion to form conduction terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bottom oxide is etched by reactive ion etch process, then electrical contact between semiconductor material and doped region is enabled, but the gate oxide may be damaged
Solution Approach 1:
A sacrificial oxide layer is introduced as an intermediary between the bottom oxide and the gate oxide. This sacrificial oxide can be selectively removed by wet etching without affecting the gate oxide, thereby enabling electrical contact while protecting the gate oxide from damage
Solution Approach 2:
The etching method is changed from reactive ion etching to wet etching for the bottom oxide removal step. This parameter change in the etching process allows selective removal of the bottom oxide while preserving the gate oxide integrity
2Reliability
If a sacrificial material cavity is formed below the transistor structure, then the bottom oxide can be removed by wet etch process, but the small diameter and total depth of the hole limit access to the cavity for etching and refilling
Solution Approach 1:
The sacrificial oxide is selectively removed from the bottom of the hole structure, extracting the problematic material that prevents electrical contact. This creates an open cavity that is accessible for subsequent semiconductor material deposition, eliminating the access problems associated with confined cavities
3Reliability
If the bottom oxide is removed to enable electrical contact, then conduction terminal formation is possible, but etching chemicals may contaminate the surfaces of the transistor
Solution Approach 1:
The sacrificial oxide serves as a protective intermediary during the wet etching process. It can be selectively removed after the transistor surfaces are formed, allowing bottom oxide removal while minimizing direct exposure of transistor surfaces to etching chemicals and reducing contamination
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of vertical MOS transistors with increased channel width, allowing higher current flow, suitable for memory cell applications like resistive and phase change memory, while minimizing contamination and access issues.
Implementation Method 1
forming a gate oxide on the inner lateral edge of the conductive layer
Implementation Method 2
forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface
Implementation Method 3
diffusing the dopants from the doped region into the semiconductor material in the hole to form a conduction terminal of the transistor
Data Source
AI summary
The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.