Vertical MOS Transistor Grooves for DRAM Cell Footprint Reduction
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Solution Overview
Problem
There is a need to improve the architectural layouts of pillar-type transistors to maintain acceptable electrical connections while achieving higher levels of integration, particularly in reducing the cell region footprint of DRAMs.
Innovation Solution
The use of vertical MOS transistors in combination with bitlines and gate electrodes within wordline grooves, where bitlines are larger than the channel width and made of metallic material, reduces wiring resistances and allows for a smaller DRAM cell region footprint by disposing gate electrodes and capacitors over the bitlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pillar-type transistors are used to achieve higher integration, then the cell region footprint is reduced, but wiring resistance increases due to smaller connection areas
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by forming bitlines in trenches below the active region and extending gate electrodes vertically along the sidewalls of the pillar. This vertical arrangement in the third dimension allows for larger effective wiring areas and better electrical connections without increasing the planar footprint, thereby reducing wiring resistance while maintaining compact cell size.
Solution Approach 2:
The patent implements a nested structure where the gate electrode is positioned within the trench containing the bitline, and the active region pillar is surrounded by the gate electrode. This nested arrangement allows multiple conductive elements to be closely integrated vertically, increasing the effective connection area between components and improving electrical connectivity without expanding the horizontal cell footprint.
2Ease of manufacture
If conventional planar layouts are used, then wiring connections are easier to maintain, but the cell region footprint becomes too large for high integration
Solution Approach 1:
The patent moves from two-dimensional planar wiring to three-dimensional wiring structures by forming trenches and vertical gate electrodes. This vertical integration allows compact cell footprints while maintaining reliable connections through increased wiring cross-sectional areas and optimized current paths in the vertical dimension.
Solution Approach 2:
The patent segments the wiring structure into distinct vertical layers: bitlines in lower trenches, channel regions in the pillar, and gate electrodes on the sidewalls. This segmentation allows each component to be independently optimized for its function while maintaining compact overall dimensions, balancing manufacturability with space efficiency.
3Reliability
If larger wiring areas are used to reduce resistance, then the cell region footprint increases, defeating the purpose of high integration
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension to increase wiring effective area. The bitline trench and vertical gate electrode structure provide larger cross-sectional areas for current flow without increasing planar footprint, thereby reducing resistance while maintaining compact cell dimensions suitable for high integration.
Data Source
AI summary
Some embodiments include semiconductor constructions having an active region surrounded by insulating material. A groove crosses the active region to divide the active region into first and second portions. A conductive wordline material is within the groove. First and second diffusion regions are within the first portion of the active region, and vertically arranged to sandwich a part of the first portion therebetween. Third and fourth diffusion regions are within the second portion of the active region, and are vertically arranged to sandwich a part of the second portion therebetween. First and second conductive regions are in electrical contact with the first and second diffusion regions, respectively. Third and fourth conductive regions are in an electrical contact with the third and fourth diffusion regions, respectively.