Vertical MOS Transistor Bottom-Up Growth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices with increasingly smaller feature sizes, as the scaling-down process complicates fabrication processes and increases manufacturing difficulties.
Innovation Solution
The method involves forming vertical Metal-Oxide-Semiconductor (MOS) transistors through specific stages, including the formation of a substrate, dielectric layer, metal lines, isolation layer, metal gate layer, and semiconductor pillars, using techniques like thermal oxidation, chemical vapor deposition, reactive ion etching, and bottom-up growth of semiconductor materials to achieve high aspect ratio structures and reduce thermal budget.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes continue to decrease to increase device density, then device scaling is achieved, but fabrication process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar 2D transistor architecture to vertical 3D architecture, enabling device stacking in the vertical dimension. This allows increased device density without proportionally increasing fabrication complexity, as the vertical structure can be formed using modified versions of existing planar fabrication processes rather than entirely new manufacturing techniques
Solution Approach 2:
The vertical transistor is divided into distinct functional segments including source region, drain region, channel region, and gate structure. This segmentation allows each region to be optimized and formed using specialized fabrication techniques appropriate to its function, simplifying the overall manufacturing process by breaking down the complex 3D structure into manageable fabrication steps
2Quantity of substance
If feature sizes decrease to increase functional density, then more devices per chip area are achieved, but reliability of individual devices becomes more difficult to maintain
Solution Approach 1:
The patent changes the geometric parameters of the transistor from planar to vertical configuration, altering the scaling relationships between different dimensions. This parameter change allows maintaining adequate channel length and width for reliability while achieving higher functional density through the vertical stacking architecture, effectively decoupling density improvements from reliability degradation
3Quantity of substance
If vertical MOS transistor structure is formed with high aspect ratio, then device density and electron mobility are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication techniques where previous fabrication steps automatically define the positioning for subsequent steps. For example, the gate structure formation is self-aligned to the channel region, and contact holes are self-aligned to the source and drain regions. This self-alignment mechanism inherently maintains the required aspect ratio precision without requiring additional external alignment procedures, thereby reducing manufacturing precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of reliable vertical MOS transistors with improved electron mobility, reduced leakage current, and increased device density, allowing for smaller device scales and better control over channel width and gate length, while maintaining structural strength and precision in metal gate formation.
Implementation Method 1
the gate dielectric layer surrounding the semiconductor pillar
Implementation Method 2
chemical vapor deposition, and bottom-up growth of semiconductor materials
Implementation Method 3
reactive ion etching
Data Source
AI summary
A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.