Vertical MOS Transistor Source Wiring with Annealing Gas Openings

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Solution Overview

Problem

Vertical transistors subjected to annealing treatment with reducing gases like hydrogen exhibit variability in properties due to the source wiring overlapping the transistor, which hinders the gas's access to the semiconductor substrate.

Innovation Solution

The semiconductor device incorporates a first source wiring with openings over the vertical transistor, allowing reducing gases to reach the substrate, thereby stabilizing the transistor properties by facilitating hydrogen termination of dangling bonds.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the first source wiring is formed to overlap with the vertical transistor to secure sufficient wiring area, then the wiring area is increased, but the reducing gas cannot easily reach the front surface of the semiconductor substrate, causing variability in transistor properties

Engineering Contradiction:
Improvewiring areaVSAvoidtransistor property consistency
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The first source wiring is segmented by forming openings (gaps) within it, allowing the reducing gas to pass through and reach the semiconductor substrate front surface. This segmentation resolves the contradiction by maintaining the overall wiring area while creating pathways for gas access, thereby ensuring consistent transistor properties during annealing treatment.

Inventive Principle:
Principle #1Segmentation

2Stability of the object's composition

If the first source wiring is made continuous without openings to ensure electrical connectivity, then the wiring integrity is maintained, but the reducing gas access to the semiconductor substrate is blocked, resulting in property variation

Engineering Contradiction:
Improvewiring integrityVSAvoidtransistor property consistency
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The first source wiring is designed with local variations: most regions maintain continuity for electrical connectivity, while specific localized openings are introduced to allow reducing gas access. This local quality modification enables the wiring to simultaneously maintain integrity and permit gas penetration, resolving the contradiction between wiring stability and transistor property consistency.

Inventive Principle:
Principle #3Local quality

3Reliability

If annealing treatment is performed with reducing gas to stabilize transistor properties through hydrogen termination, then the transistor stability is improved, but the overlapping source wiring prevents sufficient gas reachability to the substrate

Engineering Contradiction:
Improvetransistor stabilityVSAvoidgas access obstruction
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Openings are introduced into the first source wiring to segment it, creating channels through which the reducing gas can reach the semiconductor substrate front surface. This enables effective hydrogen annealing treatment for dangling bond termination, improving transistor stability while eliminating the gas access obstruction caused by the overlapping wiring.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design ensures consistent properties among vertical transistors by enabling effective hydrogen annealing treatment, reducing variability and improving transistor stability.

Implementation Method 1

dangling bonds of the semiconductor are bonded to hydrogen, so as to be terminated

Methodology Applied
Scientific EffectHydrogen termination: Chemical Bonding

Implementation Method 2

subjected to annealing treatment with a reducing gas such as hydrogen

Methodology Applied
Scientific EffectAnnealing treatment: Annealing

Data Source

PatentUS9601351B2Method of manufacturing a semiconductor device
Publication Date: 2017.03.21 RENESAS ELECTRONICS CORP
  • US9601351B2 patent drawing
  • US9601351B2 patent drawing
  • US9601351B2 patent drawing

AI summary

The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.