Vertical Power MOSFET Gate-to-Drain Capacitance Reduction
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Solution Overview
Problem
Conventional vertical power MOSFETs suffer from significant gate-to-drain capacitance and high resistance in the n-JFET region due to a large overlap area between the gate electrode and the n-JFET region, which adversely affects the device's performance, including speed and drive current.
Innovation Solution
The formation of a vertical power MOSFET with a reduced gate-to-drain capacitance is achieved by implanting a n-type doped region between the p-body regions, which is doped to a higher impurity concentration, and the use of a field plate that overlaps the n-type doped region to reduce surface electrical fields, thereby decreasing resistance and enhancing drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate electrode overlaps the n-JFET region to form a conventional vertical power MOSFET, then the device structure is simple and easy to manufacture, but the gate-to-drain capacitance increases significantly, adversely affecting speed performance
Solution Approach 1:
The patent extracts the harmful overlap area between the gate electrode and n-JFET region by introducing a trench structure. The trench physically separates the gate electrode from the n-JFET region, removing the source of gate-to-drain capacitance while maintaining the essential device functionality. This extraction approach reduces the harmful capacitance without fundamentally changing the manufacturing process complexity.
2Device complexity
If the n-JFET region is lightly doped as in conventional designs, then the device structure is simple, but the resistance of the n-JFET region becomes high, adversely affecting drive current
Solution Approach 1:
The patent applies local quality by creating a selectively doped n-type region within the n-JFET area. Instead of uniformly doping the entire n-JFET region, the invention locally increases doping concentration in specific areas (the n-type region) to reduce resistance, while maintaining lighter doping in other areas to preserve the JFET depletion region functionality. This localized differentiation resolves the contradiction between simplicity and drive current performance.
Solution Approach 2:
The patent changes the doping concentration parameter of the n-type region to a higher value compared to the conventional lightly doped n-JFET region. This parameter change directly reduces the resistance of the n-type region, thereby increasing the drive current capability of the device while maintaining the overall device structure.
3Productivity
If a higher doping concentration is applied to the n-type region to reduce resistance and increase drive current, then the drive current improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary doping action during the epitaxial growth process to form the n-type region with higher doping concentration. By incorporating the dopant during epitaxy rather than through subsequent implantation steps, the invention achieves precise doping profiles with better control over concentration and depth distribution. This preliminary action reduces the need for complex post-processing steps and maintains manufacturing precision while achieving the desired drive current improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces gate-to-drain capacitance and increases the drive current of the vertical power MOSFET by improving the doping concentration of the n-type region and using a field plate to manage surface electrical fields.
Implementation Method 1
implanting a n-type doped region between the p-body regions, which is doped to a higher impurity concentration
Implementation Method 2
the use of a field plate that overlaps the n-type doped region to reduce surface electrical fields
Data Source
AI summary
A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region. The device further includes a MOS containing device.