Vertical Source/Drain MOSFET Structure for Higher Current Density
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Solution Overview
Problem
Existing semiconductor structures, such as MOSFETs, face challenges in increasing current density without expanding their lateral footprint, which is crucial for enhancing device performance in electronic devices.
Innovation Solution
The semiconductor structure is fabricated by forming a recess in a semiconductor layer, creating a second source/drain region within the recess, and designing the path between the source/drain regions to include a substantially vertical portion, thereby increasing the path length without expanding the device's lateral footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the lateral footprint of the device is increased to accommodate longer source/drain paths, then current density increases, but the device area expands
Solution Approach 1:
The patent transitions from a two-dimensional lateral path to a three-dimensional vertical path by forming a recess in the semiconductor layer. The source/drain path extends vertically through the recess depth, allowing increased path length without increasing lateral footprint. This dimensional change enables higher current density while maintaining compact device area.
2Productivity
If the source/drain path length is increased to improve current handling, then current density increases, but the device complexity increases
Solution Approach 1:
The source/drain path is segmented into distinct regions: a first source/drain region at the upper surface, a second source/drain region at the bottom of the recess, and intermediate regions along the sidewalls. This segmentation allows the path to be constructed using standard semiconductor fabrication techniques applied to different zones, managing complexity through modular construction.
Solution Approach 2:
The recess structure nests the second source/drain region within the semiconductor layer volume, creating a vertical hierarchy. The first source/drain region sits at the upper surface, while the second region is nested deeper in the recess, forming a compact three-dimensional configuration that increases path length without proportionally increasing overall device volume.
Data Source
AI summary
A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer comprising a first uppermost surface, a lowermost surface, and a first sidewall surface extending between the uppermost surface and the lowermost surface. A gate dielectric layer is over the semiconductor layer. A first gate electrode is over a portion of the gate dielectric layer over the uppermost surface of the semiconductor layer. A first source/drain region is in the semiconductor layer under the first uppermost surface and adjacent the first gate electrode. A second source/drain region is in the semiconductor layer under the lowermost surface of the semiconductor layer.