Vertical Power MOSFET Thin Epitaxial Layer Etching
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Solution Overview
Problem
The challenge lies in manufacturing power transistors with reduced on resistance while maintaining high blocking voltage and current ratings within a compact semiconductor material, particularly in vertical power MOSFETs, where the epitaxial layer resistance is a primary factor.
Innovation Solution
A method involving a semiconductor chip with contact elements on one face and a first layer between this face and an opposing face, where the chip is placed on a carrier and etched until the first layer is reached, allowing for a thin epitaxial layer and reduced on resistance, and the drain contact is selectively spaced to fit a specific footprint on a printed circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the epitaxial layer is made thinner to decrease on resistance, then the on resistance decreases, but the blocking voltage capability may be compromised
Solution Approach 1:
The patent changes the physical parameters of the semiconductor structure by reducing epitaxial layer thickness to specific ranges (e.g., 5-20 micrometers) and adjusting doping concentrations to optimize the balance between low on-resistance and high blocking voltage capability. This involves precise control of layer thickness, doping profiles, and material composition to achieve the desired electrical characteristics.
2Manufacturing precision
If the semiconductor chip is etched to a thin epitaxial layer, then the on resistance decreases, but the structural integrity and manufacturing complexity increase
Solution Approach 1:
The patent applies preliminary actions by forming protective layers and defining etch stop layers before the thinning process. The etch stop layer is introduced at a specific depth to prevent over-etching, and protective structures are prepared in advance to guide the etching process accurately, thereby simplifying the overall manufacturing control.
Solution Approach 2:
The patent introduces an etch stop layer as an intermediary element between the epitaxial layer and the substrate. This intermediary layer facilitates controlled etching by providing a distinct stopping point, enabling precise thickness control of the epitaxial layer without requiring extremely complex real-time monitoring systems.
3Area of stationary object
If contact elements are positioned closer together to reduce footprint, then the device size decreases, but the risk of short circuits and manufacturing difficulty increase
Solution Approach 1:
The patent resolves the footprint constraint by transitioning to a vertical power MOSFET structure where current flows vertically through the device rather than laterally. This dimensional change allows contact elements to be positioned closer together in the planar footprint while maintaining adequate spacing, as the current path extends in the vertical dimension through the epitaxial layer thickness.
Solution Approach 2:
The patent employs asymmetric contact element positioning and sizing optimized for vertical current flow. The source and drain contacts are configured with asymmetric geometries and spacing that accommodate the vertical field effect transistor structure, allowing compact footprint while preventing short circuits through optimized asymmetric layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of thin semiconductor devices with lower on resistance, suitable for high-power applications, by etching the semiconductor chip to a thin epitaxial layer and strategically positioning the drain contact for efficient heat dissipation and compatibility with printed circuit boards.
Implementation Method 1
etching the semiconductor chip until the first layer is reached
Data Source
AI summary
A method of manufacturing a semiconductor device. The method includes providing a semiconductor chip including contact elements on a first face and a first layer between the first face and a second face opposite the first face. Placing the semiconductor chip on a carrier with the contact elements facing the carrier and etching the semiconductor chip until the first layer is reached.