Vertical Power MOSFET Gate-Drain Capacitance Reduction
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Solution Overview
Problem
Conventional vertical power MOSFETs suffer from significant gate-to-drain capacitance and high resistance in the n-JFET region due to a large overlap area between the gate electrode and the n-JFET region, which adversely affects performance, including speed and drive current.
Innovation Solution
The formation of a vertical power MOSFET involves a lightly doped n-type epitaxy region with self-aligned NDD regions to minimize gate-to-drain capacitance and the use of a deep metal via to reduce bulk resistance, along with a conductive field plate and source electrode configuration that minimizes overlap and enhances conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode is positioned over the n-JFET region to control the channel, then the gate can effectively modulate the source-to-drain current, but the large overlap area between the gate electrode and n-JFET region creates significant gate-to-drain capacitance that adversely affects device speed and performance
Solution Approach 1:
The patent transitions from a planar gate-to-drain overlap configuration to a vertically stacked configuration where the drain region is positioned above the gate electrode. This dimensional change eliminates the lateral overlap between gate and drain, thereby reducing gate-to-drain capacitance while preserving the vertical electric field necessary for effective current control.
Solution Approach 2:
The device structure is segmented into distinct vertical regions: the source region at the bottom, the gate electrode in the middle, and the drain region at the top. This segmentation separates the gate and drain in the vertical dimension, preventing their overlap and reducing parasitic capacitance while maintaining functional independence of each region.
2Device complexity
If the n-JFET region is lightly doped to form part of the n-type epitaxy region, then the device structure is simplified, but the resistance of the n-JFET region becomes high which adversely affects the drive current of the vertical power MOSFET
Solution Approach 1:
The patent applies different doping concentrations to different regions: the n-JFET region maintains light doping for structural simplicity and junction field effect transistor functionality, while the drain region is heavily doped to provide low resistance contact and high drive current capability. This local differentiation of doping quality resolves the contradiction between structural simplicity and electrical performance.
Solution Approach 2:
The patent changes the doping concentration parameter from uniform light doping to a graded structure where the drain region has high doping concentration (10^19 to 10^21 atoms/cm³) while the n-JFET region remains lightly doped. This parameter change in the drain region reduces resistance and enhances drive current without complicating the overall device structure.
Data Source
AI summary
A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A conductive via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the conductive via.