Vertical MOSFET with Integrated Capacitor Region
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Solution Overview
Problem
Current semiconductor packages with serially connected power MOSFETs face inefficiencies due to high package and loop inductance, leading to slow switching speeds and voltage spikes, which increase manufacturing complexity and costs, and negatively impact performance.
Innovation Solution
Integration of a vertical capacitor on the same die as the MOSFETs within the semiconductor package, utilizing existing trench isolation processes to form a high-capacity capacitor without additional manufacturing steps, reducing overall footprint and enhancing capacitance per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If discrete semiconductor components are used in PCBs to achieve desired functionality, then design flexibility is improved, but package and loop inductance increases, leading to slower switching speeds and voltage spikes
Solution Approach 1:
The patent combines multiple discrete semiconductor components (MOSFETs, diodes, capacitors) into a single integrated power module package. The MOSFETs are arranged in a planar configuration on a common substrate with integrated parasitic capacitance structures, eliminating the need for separate discrete components and their associated package inductances. This merging directly resolves the contradiction by maintaining design flexibility through integrated functionality while dramatically reducing package inductance to improve switching speed.
2Speed
If package inductance is reduced by integrating components, then switching speed is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs a universal planar substrate structure that serves multiple functions simultaneously: it acts as the mechanical support for mounting MOSFETs, provides the electrical connection network through patterned metallization layers, and incorporates parasitic capacitance structures as integral parts of the circuit functionality. This multi-functionality reduces manufacturing complexity by eliminating the need for separate capacitor components and complex interconnection structures, while achieving low package inductance for improved switching speed.
Solution Approach 2:
The patent transitions from traditional three-dimensional vertical stacking of discrete components to a two-dimensional planar configuration on a common substrate. This dimensional change allows for optimized current paths with minimal loop areas, reducing package inductance. The planar layout also simplifies manufacturing processes compared to complex vertical interconnections, resolving the contradiction between improved switching speed and reduced manufacturing complexity.
3Productivity
If source inductance is reduced to improve di/dt, then voltage spikes increase, requiring higher voltage MOSFETs and increasing cost
Solution Approach 1:
The patent incorporates parasitic capacitance structures (such as capacitive pads and inter-layer capacitance) directly into the power module package before switching events occur. These pre-integrated capacitance structures act as local energy reservoirs that suppress voltage spikes generated during rapid current changes. By having this capacitance already in place within the low-inductance package structure, the system can achieve high di/dt without requiring oversized MOSFET voltage ratings, thus resolving the contradiction between improved productivity and reduced harmful voltage spikes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces total circuit inductance, minimizes voltage spikes, and improves switching speed while maintaining compactness and reducing manufacturing costs by integrating the capacitor directly with the MOSFETs, thus enhancing the performance and efficiency of the semiconductor package.
Implementation Method 1
a vertical capacitor region adjacent to said vertical transistor region, a first plate of said vertical capacitor region comprising the source or drain region separated from the semiconductor region by the substrate
Data Source
AI summary
A method to manufacture a vertical capacitor region that comprises a plurality of trenches, wherein the portions of the semiconductor region in between the trenches comprise an impurity. This allows for the trenches to be placed in closer vicinity to each other, thus improving the capacitance per unit area ratio. The total capacitance of the device is defined by two series components, that is, the capacitance across the dielectric liner, and the depletion capacitance of the silicon next to the trench. An increase of the voltage on the capacitor increases the depletion in the silicon and the depletion capacitance as a result, such that the overall capacitance is reduced. This effect may be countered by minimizing the depletion region which may be achieved by ensuring that the silicon adjacent to the capacitor is as highly doped as possible.