Vertical Power MOSFET Structure Using Stress-Induced Layer Separation
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Solution Overview
Problem
Semiconductor substrates need to be thick for handling but this thickness degrades electrical performance, and existing techniques like SOI wafers are costly and limited in electrical performance, necessitating methods for fabricating electronic devices with reduced leakage and enhanced drive current, especially for vertical power switching devices.
Innovation Solution
The fabrication of electronic devices with a substrate having vertical sidewall regions, a gate dielectric and electrode structure, and a body region that can be fully depleted, using stress-induced separation techniques to form a semiconductor layer with a textured surface, enabling efficient charge control and reduced substrate thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the substrate is made thick for handling in production lines, then the mechanical strength and ease of handling are improved, but the electrical performance deteriorates due to increased resistance
Solution Approach 1:
The substrate is segmented into two parts: a thick substrate portion for mechanical strength and handling, and a thin semiconductor layer for electrical performance. This is achieved through stress-induced separation that divides the original substrate into a handled substrate and a separated semiconductor layer containing the device structure.
Solution Approach 2:
The semiconductor layer is extracted from the thick substrate through stress-induced separation. This extracted layer contains the channel, source, and drain regions, allowing the device to achieve low resistance electrical performance while the remaining thick substrate provides mechanical support for handling.
2Reliability
If mechanical thinning techniques are used to reduce substrate thickness, then the electrical performance is improved, but the manufacturing complexity and handling difficulty increase
Solution Approach 1:
The semiconductor layer is prepared with the complete device structure (channel, source, drain regions) before separation from the substrate. The stress-induced separation is performed as a preliminary action that releases the thin layer with pre-formed device structures, avoiding the need for complex post-separation processing.
Solution Approach 2:
Traditional mechanical thinning methods (grinding, etching) are replaced with stress-induced separation. This substitution eliminates complex mechanical processing steps while achieving the same thinning effect, simplifying the manufacturing process and improving ease of manufacture.
3Reliability
If SOI wafers are used to achieve thin substrate effects, then the electrical performance is improved, but the cost increases and applicability to vertical power switching devices is limited
Solution Approach 1:
The method uses the substrate's own stress properties to achieve separation, eliminating the need for expensive SOI wafer fabrication processes. The stress-induced separation leverages inherent material properties rather than requiring costly pre-fabricated SOI structures, reducing manufacturing cost while achieving similar electrical performance benefits.
Solution Approach 2:
The approach changes the key parameter from using pre-fabricated SOI wafers with specific thicknesses to using stress-controlled separation that can produce varying thin layer thicknesses. This parameter change enables cost-effective fabrication and allows adaptation to vertical power switching device geometries that SOI wafers cannot accommodate.
4Reliability
If the substrate is made thin to reduce resistance, then the electrical performance is improved, but the mechanical strength and handling capability deteriorate
Solution Approach 1:
The system is segmented into a thin semiconductor layer for electrical performance and a thick substrate for mechanical strength. The stress-induced separation creates this functional segmentation, allowing each part to optimize its respective property without compromising the other.
Solution Approach 2:
The stress-induced separation process acts as an intermediary mechanism that enables the transition from a single thick substrate to a combined system of thin semiconductor layer and thick substrate. This intermediary process achieves both low resistance (through thin layer) and high mechanical strength (through thick substrate) simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of electronic devices with improved electrical performance, reduced leakage, and enhanced drive current, enabling the production of devices like Power MOSFETs and IGBTs with efficient charge depletion, overcoming the limitations of traditional substrate thickness and handling costs.
Implementation Method 1
A first semiconductor layer having a surface with characteristic texture is formed by inducing stress in the substrate and separating the first semiconductor layer and the first metallic layer from a second portion of the substrate
Data Source
AI summary
A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first side of the substrate.