Vertical MOSFET Semiconductor Package for Smaller Footprint
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Solution Overview
Problem
Existing semiconductor devices for power conversion circuits occupy a large lateral area due to the need for close spacing of transistors and increased stray inductivities, limiting the miniaturization of packages and impacting performance.
Innovation Solution
A method is developed to fabricate a single semiconductor device with a vertical MOSFET configuration, where trenches are formed in a semiconductor wafer, filled with conductive material, and a polymer layer is applied to create a conductive via for direct electrical connection between the source and drain, allowing for closer chip spacing and reduced package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple semiconductor devices are accommodated in separate packages with external conductive redistribution structures, then electrical coupling between devices is achieved, but the lateral area occupied is undesirably large
Solution Approach 1:
The patent merges multiple semiconductor devices (first and second transistor devices) into a single integrated semiconductor device structure. The devices are formed on the same semiconductor substrate with shared isolation regions, and their electrical connections are established through integrated conductive structures within the same package footprint, eliminating the need for separate packages and external redistribution structures.
Solution Approach 2:
The patent transitions from a planar arrangement of separate packages to a three-dimensional integrated structure where conductive vias extend vertically through the substrate to connect different device layers. This vertical integration approach reduces lateral area occupation by utilizing the depth dimension for electrical connections.
2Area of stationary object
If transistor devices are spaced closely to reduce lateral area, then package size is reduced, but stray inductivities increase
Solution Approach 1:
The patent introduces intermediate conductive structures (conductive vias and connection regions) that mediate the electrical connection between closely spaced transistor devices. These intermediate structures provide low-inductance pathways for current flow, enabling close device spacing without significant increases in stray inductivity.
Solution Approach 2:
The patent segments the conductive connection path into multiple sections (source contact, conductive via, intermediate connection region, drain contact) that are strategically positioned to minimize loop area and inductance. This segmented approach allows optimization of each connection segment to reduce overall stray inductivity.
Data Source
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Figure 3A~3B
AI summary
In an embodiment, a semiconductor package comprises a first transistor device comprising a first surface and a second surface opposing the first surface, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. The semiconductor package further comprises a first metallization structure arranged on the first surface, the first metallization structure comprising a plurality of outer contact pads, the outer contact pads comprising a protective layer of solder, Ag or Sn, a second metallization structure arranged on the second surface, a conductive connection extending from the first surface to the second surface and electrically connecting the second power electrode to an outer contact pad of the first metallization structure, and a first epoxy layer arranged on side faces and on the first surface of the transistor device, the first epoxy layer comprising openings defining the lateral size of the outer contact pads and a package footprint.