Vertical MOSFET Pad Layout for Lower Conduction Resistance
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Solution Overview
Problem
Semiconductor devices mounted on substrates face challenges in efficiently managing high-current flows, leading to increased conduction resistance and heat dissipation issues, particularly during high-current charging in mobile devices.
Innovation Solution
A semiconductor device with a chip-size package type configuration, featuring two vertical MOS transistors and a semiconductor substrate acting as a common drain region, is face-down mounted on a substrate with strategically positioned source and gate pads, allowing for efficient current flow and reduced conduction resistance by optimizing the current path and wiring layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a semiconductor device is mounted on a mounting substrate to switch a current path, then the device can control current flow between conducting and non-conducting states, but conduction resistance increases and heat dissipation becomes problematic during high-current operations
Solution Approach 1:
The patent divides the semiconductor layer into multiple regions (first internal region, second internal region, first upper surface region, second upper surface region) with distinct functions. The semiconductor substrate serves as a common drain region that segments the current path, allowing efficient current distribution while reducing overall conduction resistance. This segmentation enables the device to handle high currents more effectively by distributing the current flow across multiple pathways.
2Loss of energy
If the current path is designed to allow efficient current flow with reduced conduction resistance, then heat dissipation is improved, but the device complexity increases due to optimized wiring layout and pad positioning
Solution Approach 1:
The patent merges the drain regions of the first and second vertical MOS transistors into a common drain region formed by the semiconductor substrate. This merging simplifies the overall structure by eliminating the need for separate drain regions and associated wiring, thereby reducing device complexity while maintaining efficient heat dissipation and current flow paths.
Solution Approach 2:
The patent utilizes the vertical dimension by forming vertical MOS transistors that extend through the semiconductor layer thickness. The source pads and gate pads are positioned on the upper surface, while the drain region is formed in the semiconductor substrate below, creating a three-dimensional current path that optimizes both electrical performance and thermal management without increasing planar complexity.
3Volume of moving object
If vertical MOS transistors are used in a chip-size package configuration, then the device achieves compact form factor for face-down mounting, but the arrangement of source pads and gate pads becomes more constrained
Solution Approach 1:
The patent employs asymmetric positioning of the first and second upper surface regions relative to the semiconductor layer. The first upper surface region contains source pads and gate pads for the first vertical MOS transistor, while the second upper surface region contains corresponding pads for the second transistor. This asymmetric arrangement optimizes the use of available chip area, ensuring proper electrical connections while maintaining a compact form factor suitable for face-down mounting applications.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.