Vertical MOSFET Array Structure for Short-Channel Control
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Solution Overview
Problem
As semiconductor processes become more refined, the size of transistors decreases, leading to a short channel effect characterized by threshold voltage variation, carrier velocity saturation, and deterioration of subthreshold characteristics, necessitating methods to overcome these challenges.
Innovation Solution
A semiconductor device is designed with a dielectric wall perpendicular to the substrate, featuring multiple metal oxide field effect transistors (MOSFETs) in direct contact with the dielectric wall, including a first MOSFET on one side surface, a second MOSFET above the first in a perpendicular direction, and a third MOSFET in parallel on the opposite side surface, utilizing 2D semiconductor materials for the channel sheets to reduce channel length and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor size is reduced to increase integration density, then area scaling is improved, but short channel effect deteriorates
Solution Approach 1:
The patent transitions from planar transistor layout to vertical stacking architecture, where multiple transistor layers are stacked in the vertical dimension perpendicular to the substrate. This allows increased integration density without further reducing the lateral footprint of individual transistors, thereby maintaining acceptable channel lengths while achieving higher area scaling.
Solution Approach 2:
The patent implements nested transistor structures where source and drain regions are positioned in different vertical layers, with channel sheets stacked between them. Multiple transistor components are nested within each other vertically, allowing compact integration while preserving sufficient horizontal channel dimensions to mitigate short channel effects.
2Length of moving object
If channel length is reduced to increase integration, then area scaling is improved, but threshold voltage control deteriorates
Solution Approach 1:
The patent extends the channel structure into the vertical dimension through stacked channel sheets, allowing the effective channel length to be maintained in the lateral direction while achieving compact integration through vertical stacking. This preserves gate control over the channel despite reduced overall device footprint.
Solution Approach 2:
The patent employs composite channel structures consisting of multiple channel sheets with different material compositions (e.g., SiGe, SiC, diamond-like carbon) stacked together. Each layer can be independently engineered to optimize electrical characteristics, allowing precise control of threshold voltage and carrier mobility while maintaining adequate effective channel length.
Data Source
AI summary
A semiconductor device includes a dielectric wall provided in a direction perpendicular to a substrate, a first metal oxide field effect transistor (MOSFET) provided on one side surface of the dielectric wall, a second MOSFET provided above the first MOSFET in a direction perpendicular to the substrate, and a third MOSFET provided in parallel with the first MOSFET on the other side surface of the dielectric wall.