Vertical MOSFET SRAM Cell Gate-All-Around Structure
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Solution Overview
Problem
Conventional transistors with horizontal channels face challenges in increasing integrated circuit density and efficiency due to short channel effects, which degrade their operating characteristics.
Innovation Solution
The semiconductor device employs a vertical MOSFET SRAM cell with a gate-all-around structure and adjustable channel dimensions, utilizing different thicknesses and materials for the patterns and gate electrodes to control current ratios and reduce the short channel effect, thereby improving carrier mobility and transistor efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistors with horizontal channels are used, then the device structure is simple and easy to manufacture, but the integrated circuit density cannot be increased and short channel effects degrade operating characteristics
Solution Approach 1:
The patent transitions from conventional horizontal channel transistors to vertical channel transistors, changing the dimension of current flow from in-plane to out-of-plane. This vertical configuration allows multiple transistor layers to be stacked, dramatically increasing integration density while maintaining manufacturability through established semiconductor processing techniques adapted for vertical structures.
Solution Approach 2:
The patent implements a gate-all-around structure where the gate electrode completely surrounds the channel region in three dimensions. This nested configuration provides superior electrostatic control over the channel, effectively suppressing short channel effects while enabling smaller transistor footprints and higher density integration.
2Reliability
If vertical MOSFET with gate-all-around structure is used, then short channel effect is reduced and carrier mobility is improved, but the device structure becomes more complex
Solution Approach 1:
The gate-all-around structure nests the gate electrode completely around the channel region, providing 360-degree electrostatic control. This nested configuration suppresses short channel effects by preventing field penetration from the drain to source, thereby improving transistor reliability and operating characteristics despite the increased structural complexity.
Solution Approach 2:
The patent employs different materials and thicknesses for various gate electrode portions to optimize local electrostatic control. By tailoring the gate structure's properties at different locations around the channel, the design achieves superior overall performance while managing the complexity through localized optimizations rather than uniform structure changes.
3Area of moving object
If vertical MOSFET with adjustable channel dimensions is used, then current ratio between transistors can be controlled and cell size is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
By transitioning to vertical channel transistors, the patent reduces the in-plane footprint of each transistor, allowing smaller SRAM cell areas. The vertical dimension provides an additional degree of freedom for controlling channel characteristics through height adjustment, enabling area reduction while managing manufacturing precision through the extra dimensional control parameter.
Solution Approach 2:
The patent utilizes adjustable channel dimensions (width and height) as key parameters to control transistor characteristics and current ratios. By varying these dimensional parameters during design and manufacturing, the system achieves precise control over transistor behavior and minimizes cell size while accommodating manufacturing variations through parameter optimization.
Data Source
AI summary
A semiconductor device includes a substrate, a first pattern, a first gate electrode, and a second pattern. The first pattern is disposed on the substrate and extends in a first direction substantially vertical to an upper surface of the substrate, and includes a first part, a second part and a third part sequentially disposed on the substrate. The first gate electrode is connected to the second part and extends in a second direction different from the first direction. The second pattern is disposed on the substrate, extends in the first direction, is connected to the first part, and does not contact the first gate electrode.