Vertical MOSFET Super Junction Depth Control via Pre-Formed Trenches
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Solution Overview
Problem
The existing manufacturing processes for semiconductor devices with a super junction (SJ) structure face challenges in achieving precise depth control of PN columns, leading to variations in breakdown voltage and device characteristics, and involve complex and costly processing steps that can result in crystal defects and increased manufacturing costs.
Innovation Solution
The method involves forming a concave portion in the semiconductor layer before epitaxial growth, allowing the second semiconductor layer to be embedded within trenches and the concave portion, thereby simplifying the process and eliminating the need for subsequent polishing and cleaning steps, which helps in maintaining precise depth control and reducing variations in device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If flattening and polishing is performed after epitaxial growth to form PN columns, then the surface can be made flat, but the depths of PN columns vary and cannot reach desired depth with high precision
Solution Approach 1:
The patent forms a predetermined-depth trench before epitaxial growth, establishing the final PN column depth boundary in advance. This preliminary action eliminates the need for post-growth polishing and ensures precise depth control without affecting surface flatness
Solution Approach 2:
Instead of growing the PN column to full depth then removing excess material through polishing, the patent inverts the approach by pre-forming a trench of the exact desired depth and growing the PN column only within this confined space, thereby achieving precision without material removal
2Reliability
If multiple processing steps including polishing and cleaning are performed between SJ structure formation and p-type layer growth, then the surface can be prepared, but crystal defects occur and p-type layer grows abnormally
Solution Approach 1:
The patent performs preliminary cleaning and surface preparation immediately after trench formation and before epitaxial growth. This timing ensures the surface is clean for growth without requiring subsequent processing steps that could introduce defects or abnormal growth
Solution Approach 2:
The patent combines multiple functions (trench formation, surface preparation, and depth definition) into a single integrated process sequence, eliminating the need for separate polishing and cleaning steps between SJ structure formation and p-type layer growth
3Ease of manufacture
If independent processing is performed for forming p-type layer on SJ structure, then the layer can be formed, but manufacturing costs rise with increase in number of manufacturing processes
Solution Approach 1:
The patent merges the formation of the p-type layer with the SJ structure formation process by pre-forming trenches that define both the PN column boundaries and the p-type layer growth region. This integration allows both structures to be formed in a coordinated manner, reducing the number of independent processing steps and manufacturing costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces variations in breakdown voltage, and improves device characteristics by eliminating the need for complex polishing and cleaning steps, thereby enhancing the reliability and efficiency of semiconductor device production.
Implementation Method 1
a second semiconductor layer is epitaxially grown within a trench formed in a first semiconductor layer to form the SJ structure
Data Source
AI summary
A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate.