Vertical MOSFET Superlattice Charge Carrier Mobility
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Solution Overview
Problem
Despite advancements in materials engineering, semiconductor devices still require improved charge carrier mobility to enhance device speed and reduce power consumption, especially as devices shrink and new configurations emerge.
Innovation Solution
A semiconductor device with a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) incorporating a superlattice structure, where layers of semiconductor and non-semiconductor monolayers are laterally stacked, enhancing band-engineered properties and charge carrier transport in the vertical direction, with a gate surrounding the superlattice and dielectric layers for improved mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional semiconductor materials and structures are used, then device fabrication is straightforward, but charge carrier mobility is limited
Solution Approach 1:
The channel region is segmented into multiple alternating layers of different semiconductor materials (e.g., SiGe and Si) forming a superlattice structure. This segmentation creates distinct regions with different band structures that collectively enhance charge carrier mobility through reduced effective mass and suppressed scattering mechanisms.
Solution Approach 2:
The patent employs composite semiconductor materials in the superlattice structure, combining materials like SiGe and Si with complementary properties. The composite structure leverages the advantages of each material to achieve enhanced mobility while maintaining structural integrity and compatibility with existing semiconductor fabrication processes.
2Productivity
If device dimensions are reduced to continue scaling, then device density increases, but charge carrier mobility degrades
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically stacked 3D superlattice channels. This dimensional change allows the channel to extend in the vertical direction while maintaining control over carrier transport, effectively increasing device density without sacrificing mobility in the lateral transport direction.
Solution Approach 2:
The superlattice structure enables independent optimization of multiple parameters: layer thicknesses, material compositions, and stacking sequences can be tuned to maintain high mobility while reducing the lateral footprint. The vertical stacking allows increased effective channel area without increasing planar device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The superlattice structure reduces the effective mass of charge carriers, leading to increased mobility and other structural advantages, such as reduced scattering effects and potential for piezoelectric, pyroelectric, and ferroelectric properties, enhancing device performance and functionality.
Implementation Method 1
enhancing band-engineered properties and charge carrier transport in the vertical direction
Implementation Method 2
causing transport of charge carriers through the at least one superlattice in the vertical direction
Implementation Method 3
reduced scattering effects
Data Source
AI summary
A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.