Vertical MOSFET Trench Structure Reducing Parasitic Capacitance
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Solution Overview
Problem
High voltage metal-oxide-semiconductor field-effect transistors (MOS FETs) with vertical structures face challenges in reducing parasitic capacitance and switching loss, which affect their operation speed.
Innovation Solution
The design involves a vertical transistor cell with a trench structure, where conductive features are buried in an insulator, and the overlapping distance and extended length of these features are optimized to reduce parasitic capacitance, enhancing operation speed and switching efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a vertical MOS transistor structure is used to withstand greater drain-to-source voltage difference and current level, then the device can handle higher power applications, but parasitic capacitance increases which reduces operation speed
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a vertical three-dimensional structure. The source and drain are positioned one over another vertically, allowing the transistor to withstand higher voltages and currents while reducing the overlapping area between conductive features, thereby reducing parasitic capacitance and improving switching speed.
Solution Approach 2:
The patent divides the transistor structure into distinct vertical segments including a trench region, an insulator layer, and conductive features at different depths. This segmentation allows optimization of each region's function - the trench provides mechanical support and electrical isolation, the insulator reduces parasitic capacitance, and the conductive features are positioned to minimize overlap while maintaining electrical connectivity.
2Area of stationary object
If conductive features are positioned closer together to reduce device area, then area efficiency improves, but parasitic capacitance increases reducing switching efficiency
Solution Approach 1:
The patent utilizes the vertical dimension to separate conductive features that would otherwise need to be spaced apart in a planar configuration. By positioning conductive features at different vertical levels with an insulator layer between them, the design achieves compact area utilization while maintaining low parasitic capacitance through reduced overlapping area.
Data Source
AI summary
A method of forming a manufacture includes forming a trench in a doped layer; and forming a gate dielectric layer along sidewalls of an upper portion of the trench. The method further includes forming a first conductive feature along sidewalls of the gate dielectric layer, wherein the first conductive feature has a first depth in the trench. The method further includes forming an insulating layer covering the first conductive feature and the first insulating layer. The method further includes forming a second conductive feature along sidewalls of the second insulating layer, wherein the second conductive feature has a second depth in the trench different from the first depth.